diff mbox

[rs6000] Fix PR78604

Message ID 2d7b81d0-41e8-a194-9c09-442e3e9d0e35@linux.vnet.ibm.com
State New
Headers show

Commit Message

Pat Haugen Feb. 8, 2017, 6:45 p.m. UTC 
The following patch fixes the pr by adding code for integer comparisons to invert the condition and swap operands to avoid generation of a compound test. Bootstrap/regtest on powerpc64-unknown-linux-gnu with no new regressions. Ok for trunk?

-Pat


2017-02-08  Pat Haugen  <pthaugen@us.ibm.com>

	PR target/78604
	* config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Invert
	condition/operands for integer GE/LE/GEU/LEU operations.


testsuite/ChangeLog:
2017-02-08  Pat Haugen  <pthaugen@us.ibm.com>

	PR target/78604
	* gcc.target/powerpc/pr78604.c: New.

Comments

Segher Boessenkool Feb. 8, 2017, 7:52 p.m. UTC | #1 
On Wed, Feb 08, 2017 at 12:45:22PM -0600, Pat Haugen wrote:
> The following patch fixes the pr by adding code for integer comparisons to invert the condition and swap operands to avoid generation of a compound test. Bootstrap/regtest on powerpc64-unknown-linux-gnu with no new regressions. Ok for trunk?

This had me confused for a bit, but you're not swapping the operands of
the condition, you're swapping the true/false operands of the cond
expression :-)
Okay for trunk.  Thanks,


Segher


> 2017-02-08  Pat Haugen  <pthaugen@us.ibm.com>
> 
> 	PR target/78604
> 	* config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Invert
> 	condition/operands for integer GE/LE/GEU/LEU operations.
> 
> 
> testsuite/ChangeLog:
> 2017-02-08  Pat Haugen  <pthaugen@us.ibm.com>
> 
> 	PR target/78604
> 	* gcc.target/powerpc/pr78604.c: New.
diff mbox

Patch

Index: config/rs6000/rs6000.c
===================================================================
--- config/rs6000/rs6000.c	(revision 245252)
+++ config/rs6000/rs6000.c	(working copy)
@@ -25150,12 +25150,29 @@  rs6000_emit_vector_cond_expr (rtx dest,
 	return 0;
       break;
 
-      /* Mark unsigned tests with CCUNSmode.  */
+    case GE:
+    case LE:
+      if (GET_MODE_CLASS (mask_mode) == MODE_VECTOR_INT)
+	{
+	  /* Invert condition to avoid compound test.  */
+	  invert_move = true;
+	  rcode = reverse_condition (rcode);
+	}
+      break;
+
     case GTU:
     case GEU:
     case LTU:
     case LEU:
+      /* Mark unsigned tests with CCUNSmode.  */
       cc_mode = CCUNSmode;
+
+      /* Invert condition to avoid compound test if necessary.  */
+      if (rcode == GEU || rcode == LEU)
+	{
+	  invert_move = true;
+	  rcode = reverse_condition (rcode);
+	}
       break;
 
     default:
Index: testsuite/gcc.target/powerpc/pr78604.c
===================================================================
--- testsuite/gcc.target/powerpc/pr78604.c	(revision 0)
+++ testsuite/gcc.target/powerpc/pr78604.c	(working copy)
@@ -0,0 +1,112 @@ 
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize" } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+#ifndef ALIGN
+#define ALIGN 32
+#endif
+
+#ifndef TYPE
+#define TYPE long long
+#endif
+
+#ifndef SIGN_TYPE
+#define SIGN_TYPE signed TYPE
+#endif
+
+#ifndef UNS_TYPE
+#define UNS_TYPE unsigned TYPE
+#endif
+
+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))
+
+SIGN_TYPE	sa[SIZE] ALIGN_ATTR;
+SIGN_TYPE	sb[SIZE] ALIGN_ATTR;
+SIGN_TYPE	sc[SIZE] ALIGN_ATTR;
+
+UNS_TYPE	ua[SIZE] ALIGN_ATTR;
+UNS_TYPE	ub[SIZE] ALIGN_ATTR;
+UNS_TYPE	uc[SIZE] ALIGN_ATTR;
+
+void
+sign_lt (SIGN_TYPE val1, SIGN_TYPE val2)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    sa[i] = (sb[i] < sc[i]) ? val1 : val2;
+}
+
+void
+sign_lte (SIGN_TYPE val1, SIGN_TYPE val2)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    sa[i] = (sb[i] <= sc[i]) ? val1 : val2;
+}
+
+void
+sign_gt (SIGN_TYPE val1, SIGN_TYPE val2)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    sa[i] = (sb[i] > sc[i]) ? val1 : val2;
+}
+
+void
+sign_gte (SIGN_TYPE val1, SIGN_TYPE val2)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    sa[i] = (sb[i] >= sc[i]) ? val1 : val2;
+}
+
+
+void
+uns_lt (UNS_TYPE val1, UNS_TYPE val2)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    ua[i] = (ub[i] < uc[i]) ? val1 : val2;
+}
+
+void
+uns_lte (UNS_TYPE val1, UNS_TYPE val2)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    ua[i] = (ub[i] <= uc[i]) ? val1 : val2;
+}
+
+void
+uns_gt (UNS_TYPE val1, UNS_TYPE val2)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    ua[i] = (ub[i] > uc[i]) ? val1 : val2;
+}
+
+void
+uns_gte (UNS_TYPE val1, UNS_TYPE val2)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    ua[i] = (ub[i] >= uc[i]) ? val1 : val2;
+}
+
+/* { dg-final { scan-assembler-times {\mvcmpgtsd\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mvcmpgtud\M} 4 } } */
+/* { dg-final { scan-assembler-not   {\mvcmpequd\M} } } */