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[SPARC] Fix PR target/91269

Message ID 2489709.bk7ymy2vyL@polaris
State New
Headers show
Series [SPARC] Fix PR target/91269 | expand

Commit Message

Eric Botcazou Sept. 20, 2019, 9:45 a.m. UTC 
This is a regression present on the mainline and 9 branch: the compiler (LRA) 
generates an instruction using unaligned double FP registers.  This has been a 
known weakness since the switch to LRA because there is no longer an explicit 
constraint for aligned double FP registers.

Bootstrapped/regtested on SPARC/Solaris and SPARC64/Linux, applied on the 
mainline and 9 branch.


2019-09-20  Eric Botcazou  <ebotcazou@adacore.com>

	PR target/91269
	* config/sparc/sparc.h (HARD_REGNO_CALLER_SAVE_MODE): Define.


2019-09-20  Eric Botcazou  <ebotcazou@adacore.com>

	* gcc.dg/pr91269.c: New test.
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Patch

Index: config/sparc/sparc.h
===================================================================
--- config/sparc/sparc.h	(revision 275746)
+++ config/sparc/sparc.h	(working copy)
@@ -711,6 +711,13 @@  along with GCC; see the file COPYING3.
    register window instruction in the prologue.  */
 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1)
 
+/* Select a register mode required for caller save of hard regno REGNO.
+   Contrary to what is documented, the default is not the smallest suitable
+   mode but the largest suitable mode for the given (REGNO, NREGS) pair and
+   it quickly creates paradoxical subregs that can be problematic.  */
+#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
+  ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, false) : (MODE))
+
 /* Specify the registers used for certain standard purposes.
    The values of these macros are register numbers.  */