===================================================================
@@ -8589,7 +8589,7 @@ (define_expand "vec_perm_constv8qi"
mask |= (INTVAL (XVECEXP (sel, 0, i)) & 0xf) << (28 - i*4);
sel = force_reg (SImode, gen_int_mode (mask, SImode));
- emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, const0_rtx));
+ emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, const0_rtx));
emit_insn (gen_bshufflev8qi_vis (operands[0], operands[1], operands[2]));
DONE;
})
===================================================================
@@ -11527,7 +11527,7 @@ sparc_expand_vec_perm_bmask (enum machin
}
/* Always perform the final addition/merge within the bmask insn. */
- emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, t_1));
+ emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, t_1));
}
/* Implement TARGET_FRAME_POINTER_REQUIRED. */
@@ -11766,7 +11766,7 @@ static void
vector_init_bshuffle (rtx target, rtx elt, enum machine_mode mode,
enum machine_mode inner_mode)
{
- rtx t1, final_insn;
+ rtx t1, final_insn, sel;
int bmask;
t1 = gen_reg_rtx (mode);
@@ -11792,8 +11792,8 @@ vector_init_bshuffle (rtx target, rtx el
gcc_unreachable ();
}
- emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), CONST0_RTX (SImode),
- force_reg (SImode, GEN_INT (bmask))));
+ sel = force_reg (SImode, GEN_INT (bmask));
+ emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, const0_rtx));
emit_insn (final_insn);
}
===================================================================
@@ -1,5 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-O -mcpu=ultrasparc3 -mvis -mvis2" } */
+/* { dg-options "-O -mvis2" } */
+
typedef long long int64_t;
typedef int vec32 __attribute__((vector_size(8)));
typedef short vec16 __attribute__((vector_size(8)));