[x86] Define VECTOR_STORE_FLAG_VALUE

Return constm1_rtx when GET_MODE_CLASS (MODE) == MODE_VECTOR_INT.
Otherwise NULL_RTX.

Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ready push to trunk.

gcc/ChangeLog:

	* config/i386/i386.h (VECTOR_STORE_FLAG_VALUE): New macro.

gcc/testsuite/ChangeLog:
	* gcc.dg/rtl/x86_64/vector_eq.c: New test.
---
 gcc/config/i386/i386.h                      |  5 +++-
 gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c | 26 +++++++++++++++++++++
 2 files changed, 30 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c

On Tue, Sep 24, 2024 at 11:23 AM liuhongt <hongtao.liu@intel.com> wrote:
>
> Return constm1_rtx when GET_MODE_CLASS (MODE) == MODE_VECTOR_INT.
> Otherwise NULL_RTX.
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> Ready push to trunk.
>
> gcc/ChangeLog:
>
>         * config/i386/i386.h (VECTOR_STORE_FLAG_VALUE): New macro.
>
> gcc/testsuite/ChangeLog:
>         * gcc.dg/rtl/x86_64/vector_eq.c: New test.
> ---
>  gcc/config/i386/i386.h                      |  5 +++-
>  gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c | 26 +++++++++++++++++++++
>  2 files changed, 30 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c
>
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index c1ec92ffb15..b12be41424f 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -899,7 +899,10 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
>     and give entire struct the alignment of an int.  */
>  /* Required on the 386 since it doesn't have bit-field insns.  */
>  #define PCC_BITFIELD_TYPE_MATTERS 1
> -
> +
> +#define VECTOR_STORE_FLAG_VALUE(MODE) \
> +  (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT ? constm1_rtx : NULL_RTX)
> +
>  /* Standard register usage.  */
>
>  /* This processor has special stack-like registers.  See reg-stack.cc
> diff --git a/gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c b/gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c
> new file mode 100644
> index 00000000000..b82603d0b64
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile { target x86_64-*-* } } */

target { { i?86-*-* x86_64-*-* } && lp64 }

Uros.

> +/* { dg-additional-options "-O2 -march=x86-64-v3" } */
> +
> +typedef int v4si __attribute__((vector_size(16)));
> +
> +v4si __RTL (startwith ("vregs")) foo (void)
> +{
> +(function "foo"
> +  (insn-chain
> +    (block 2
> +      (edge-from entry (flags "FALLTHRU"))
> +      (cnote 1 [bb 2] NOTE_INSN_BASIC_BLOCK)
> +      (cnote 2 NOTE_INSN_FUNCTION_BEG)
> +      (cinsn 3 (set (reg:V4SI <0>) (const_vector:V4SI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)])))
> +      (cinsn 5 (set (reg:V4SI <2>)
> +                   (eq:V4SI (reg:V4SI <0>) (reg:V4SI <1>))))
> +      (cinsn 6 (set (reg:V4SI <3>) (reg:V4SI <2>)))
> +      (cinsn 7 (set (reg:V4SI xmm0) (reg:V4SI <3>)))
> +      (edge-to exit (flags "FALLTHRU"))
> +    )
> +  )
> + (crtl (return_rtx (reg/i:V4SI xmm0)))
> +)
> +}
> +
> +/* { dg-final { scan-assembler-not "vpxor" } } */
> --
> 2.31.1
>

On Tue, Sep 24, 2024 at 5:46 PM Uros Bizjak <ubizjak@gmail.com> wrote:
>
> On Tue, Sep 24, 2024 at 11:23 AM liuhongt <hongtao.liu@intel.com> wrote:
> >
> > Return constm1_rtx when GET_MODE_CLASS (MODE) == MODE_VECTOR_INT.
> > Otherwise NULL_RTX.
> >
> > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> > Ready push to trunk.
> >
> > gcc/ChangeLog:
> >
> >         * config/i386/i386.h (VECTOR_STORE_FLAG_VALUE): New macro.
> >
> > gcc/testsuite/ChangeLog:
> >         * gcc.dg/rtl/x86_64/vector_eq.c: New test.
> > ---
> >  gcc/config/i386/i386.h                      |  5 +++-
> >  gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c | 26 +++++++++++++++++++++
> >  2 files changed, 30 insertions(+), 1 deletion(-)
> >  create mode 100644 gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c
> >
> > diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> > index c1ec92ffb15..b12be41424f 100644
> > --- a/gcc/config/i386/i386.h
> > +++ b/gcc/config/i386/i386.h
> > @@ -899,7 +899,10 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
> >     and give entire struct the alignment of an int.  */
> >  /* Required on the 386 since it doesn't have bit-field insns.  */
> >  #define PCC_BITFIELD_TYPE_MATTERS 1
> > -
> > +
> > +#define VECTOR_STORE_FLAG_VALUE(MODE) \
> > +  (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT ? constm1_rtx : NULL_RTX)
> > +
> >  /* Standard register usage.  */
> >
> >  /* This processor has special stack-like registers.  See reg-stack.cc
> > diff --git a/gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c b/gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c
> > new file mode 100644
> > index 00000000000..b82603d0b64
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c
> > @@ -0,0 +1,26 @@
> > +/* { dg-do compile { target x86_64-*-* } } */
>
> target { { i?86-*-* x86_64-*-* } && lp64 }
Thanks, changed.
>
> Uros.
>
> > +/* { dg-additional-options "-O2 -march=x86-64-v3" } */
> > +
> > +typedef int v4si __attribute__((vector_size(16)));
> > +
> > +v4si __RTL (startwith ("vregs")) foo (void)
> > +{
> > +(function "foo"
> > +  (insn-chain
> > +    (block 2
> > +      (edge-from entry (flags "FALLTHRU"))
> > +      (cnote 1 [bb 2] NOTE_INSN_BASIC_BLOCK)
> > +      (cnote 2 NOTE_INSN_FUNCTION_BEG)
> > +      (cinsn 3 (set (reg:V4SI <0>) (const_vector:V4SI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)])))
> > +      (cinsn 5 (set (reg:V4SI <2>)
> > +                   (eq:V4SI (reg:V4SI <0>) (reg:V4SI <1>))))
> > +      (cinsn 6 (set (reg:V4SI <3>) (reg:V4SI <2>)))
> > +      (cinsn 7 (set (reg:V4SI xmm0) (reg:V4SI <3>)))
> > +      (edge-to exit (flags "FALLTHRU"))
> > +    )
> > +  )
> > + (crtl (return_rtx (reg/i:V4SI xmm0)))
> > +)
> > +}
> > +
> > +/* { dg-final { scan-assembler-not "vpxor" } } */
> > --
> > 2.31.1
> >