From patchwork Mon May 13 14:55:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1934752 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=lw2WdFoG; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VdMxn5txTz1yfq for ; Tue, 14 May 2024 00:56:13 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 25DFB38708C0 for ; Mon, 13 May 2024 14:56:12 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by sourceware.org (Postfix) with ESMTPS id EC0F63849ADD for ; Mon, 13 May 2024 14:55:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EC0F63849ADD Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EC0F63849ADD Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715612153; cv=none; b=pCA1oWOEFSsMfIwkVJ2VTVxZYD7yAyfmDXRu4D3SDrLebGX+VSioqvTVMI/9CwRvWcYpsQGMaDydkOxC+BNU9MG72c9JFFbIr3LBFB6DKrn7VUR2pdyJeitVaRRO3uwbLumSAZeZV8ZyV7lE+fvx8Gkj416H13uYRQVSEyjgQM8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715612153; c=relaxed/simple; bh=otVgq7ZqOcw3l2j7QtvTUC0IgDSV0GUFs2a43sxgXyg=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=hop/jTYUnUl9heQA1DtbPTyx+MxtbAHs3rCfN7D4JAcRWtDkpfjrl0E5VfP/roDUxpuSmAIXgFzuYtACDSsJDud4loSy9cF9KxSm6zSXmTpivXhkcTJXlxGdASWX25i8fYH7aWRm8YnAUC0/zI2yJ2oESEFNVp9nBTx88rzoOzw= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715612151; x=1747148151; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=otVgq7ZqOcw3l2j7QtvTUC0IgDSV0GUFs2a43sxgXyg=; b=lw2WdFoGoFszVaqS6sBdrahoi5B6WwPg/s5xDdfb3D7xe2ZJaw+XtuF1 8bZn7ng7vkkJiXi5xR+YRyPjm7N8odTjI5lW7Mvq/yf5AjvV04Tt39Y46 J9jj9k7a23EDC+agXuLsJ/TFJfoZi/8X7HmizJ9OK6vUVMP6TpdUr29tz koYSgBGGxllNTlASit7Mfl2P9jiordO2iz9qZGKFM1/1KMl39EQiGYz5w cRr2pJcz5Z3dI8AzWGRWLS/dHoPVtOHoIJLv+mfcHKzsEUXBjMe0AGCLN u27hhKm4Js4Xvrg2WLhQoOhekPjFs8V0t+owz12ZlS6U4HzBdZ+Oq9/Yq Q==; X-CSE-ConnectionGUID: rS5Y2bheR/Ccn9VFYjxYZg== X-CSE-MsgGUID: C5ERNNzbQfCn+A0wIUqpMg== X-IronPort-AV: E=McAfee;i="6600,9927,11072"; a="22949031" X-IronPort-AV: E=Sophos;i="6.08,158,1712646000"; d="scan'208";a="22949031" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2024 07:55:49 -0700 X-CSE-ConnectionGUID: K++zRZzITma4xTimvPsQMw== X-CSE-MsgGUID: cYBe2YjlTgWfeC4QZQ2VgA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,158,1712646000"; d="scan'208";a="30763428" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orviesa006.jf.intel.com with ESMTP; 13 May 2024 07:55:47 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 7880A1005664; Mon, 13 May 2024 22:55:46 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, richard.guenther@gmail.com, Tamar.Christina@arm.com, richard.sandiford@arm.com, Pan Li Subject: [PATCH v1 2/3] RISC-V: Implement vectorizable early exit with vcond_mask_len Date: Mon, 13 May 2024 22:55:43 +0800 Message-Id: <20240513145543.149757-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch depends on below middle-end implementation. https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651459.html After we support the loop lens for the vectorizable, we would like to implement the feature for the RISC-V target. Given below example: unsigned vect_a[1923]; unsigned vect_b[1923]; unsigned test (unsigned limit, int n) { unsigned ret = 0; for (int i = 0; i < n; i++) { vect_b[i] = limit + i; if (vect_a[i] > limit) { ret = vect_b[i]; return ret; } vect_a[i] = limit; } return ret; } Before this patch: ... .L8: sw a3,0(a5) addiw a0,a0,1 addi a4,a4,4 addi a5,a5,4 beq a1,a0,.L2 .L4: sw a0,0(a4) lw a2,0(a5) bleu a2,a3,.L8 ret After this patch: ... .L5: vsetvli a5,a3,e8,mf4,ta,ma vmv1r.v v4,v2 vsetvli t4,zero,e32,m1,ta,ma vmv.v.x v1,a5 vadd.vv v2,v2,v1 vsetvli zero,a5,e32,m1,ta,ma vadd.vv v5,v4,v3 slli a6,a5,2 vle32.v v1,0(t1) vmsltu.vv v1,v3,v1 vcpop.m t4,v1 beq t4,zero,.L4 vmv.x.s a4,v4 .L3: ... The below tests are passed for this patch: 1. The riscv fully regression tests. gcc/ChangeLog: * config/riscv/autovec-opt.md (*vcond_mask_len_popcount_): New pattern of vcond_mask_len_popcount for vector bool mode. * config/riscv/autovec.md (vcond_mask_len_): New pattern of vcond_mask_len for vector bool mode. (cbranch4): New pattern for vector bool mode. * config/riscv/vector-iterators.md: Add new unspec UNSPEC_SELECT_MASK. * config/riscv/vector.md (@pred_popcount): Add VLS mode to popcount pattern. (@pred_popcount): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/early-break-1.c: New test. * gcc.target/riscv/rvv/autovec/early-break-2.c: New test. Signed-off-by: Pan Li --- gcc/config/riscv/autovec-opt.md | 33 ++++++++++ gcc/config/riscv/autovec.md | 60 +++++++++++++++++++ gcc/config/riscv/vector-iterators.md | 1 + gcc/config/riscv/vector.md | 18 +++--- .../riscv/rvv/autovec/early-break-1.c | 34 +++++++++++ .../riscv/rvv/autovec/early-break-2.c | 37 ++++++++++++ 6 files changed, 174 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-2.c diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 645dc53d868..04f85d8e455 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -1436,3 +1436,36 @@ (define_insn_and_split "*n" DONE; } [(set_attr "type" "vmalu")]) + +;; Optimization pattern for early break auto-vectorization +;; vcond_mask_len (mask, ones, zeros, len, bias) + vlmax popcount +;; -> non vlmax popcount (mask, len) +(define_insn_and_split "*vcond_mask_len_popcount_" + [(set (match_operand:P 0 "register_operand") + (popcount:P + (unspec:VB_VLS [ + (unspec:VB_VLS [ + (match_operand:VB_VLS 1 "register_operand") + (match_operand:VB_VLS 2 "const_1_operand") + (match_operand:VB_VLS 3 "const_0_operand") + (match_operand 4 "autovec_length_operand") + (match_operand 5 "const_0_operand")] UNSPEC_SELECT_MASK) + (match_operand 6 "autovec_length_operand") + (const_int 1) + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))] + "TARGET_VECTOR + && can_create_pseudo_p () + && riscv_vector::get_vector_mode (Pmode, GET_MODE_NUNITS (mode)).exists ()" + "#" + "&& 1" + [(const_int 0)] + { + riscv_vector::emit_nonvlmax_insn ( + code_for_pred_popcount (mode, Pmode), + riscv_vector::CPOP_OP, + operands, operands[4]); + DONE; + } + [(set_attr "type" "vector")] +) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index aa1ae0fe075..dfa58b8af69 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -2612,3 +2612,63 @@ (define_expand "rawmemchr" DONE; } ) + +;; ========================================================================= +;; == Early break auto-vectorization patterns +;; ========================================================================= + +;; vcond_mask_len +(define_insn_and_split "vcond_mask_len_" + [(set (match_operand:VB 0 "register_operand") + (unspec: VB [ + (match_operand:VB 1 "register_operand") + (match_operand:VB 2 "const_1_operand") + (match_operand:VB 3 "const_0_operand") + (match_operand 4 "autovec_length_operand") + (match_operand 5 "const_0_operand")] UNSPEC_SELECT_MASK))] + "TARGET_VECTOR + && can_create_pseudo_p () + && riscv_vector::get_vector_mode (Pmode, GET_MODE_NUNITS (mode)).exists ()" + "#" + "&& 1" + [(const_int 0)] + { + machine_mode mode = riscv_vector::get_vector_mode (Pmode, + GET_MODE_NUNITS (mode)).require (); + rtx reg = gen_reg_rtx (mode); + riscv_vector::expand_vec_series (reg, const0_rtx, const1_rtx); + rtx dup_rtx = gen_rtx_VEC_DUPLICATE (mode, operands[4]); + insn_code icode = code_for_pred_cmp_scalar (mode); + rtx cmp = gen_rtx_fmt_ee (LTU, mode, reg, dup_rtx); + rtx ops[] = {operands[0], operands[1], operands[1], cmp, reg, operands[4]}; + emit_vlmax_insn (icode, riscv_vector::COMPARE_OP_MU, ops); + DONE; + } + [(set_attr "type" "vector")]) + +;; cbranch +(define_expand "cbranch4" + [(set (pc) + (if_then_else + (match_operator 0 "equality_operator" + [(match_operand:VB_VLS 1 "register_operand") + (match_operand:VB_VLS 2 "reg_or_0_operand")]) + (label_ref (match_operand 3 "")) + (pc)))] + "TARGET_VECTOR" + { + rtx pred; + if (operands[2] == CONST0_RTX (mode)) + pred = operands[1]; + else + pred = expand_binop (mode, xor_optab, operands[1], + operands[2], NULL_RTX, 0, + OPTAB_DIRECT); + rtx reg = gen_reg_rtx (Pmode); + rtx cpop_ops[] = {reg, pred}; + emit_vlmax_insn (code_for_pred_popcount (mode, Pmode), + riscv_vector::CPOP_OP, cpop_ops); + operands[1] = reg; + operands[2] = const0_rtx; + } +) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index a24e1bf078f..76c27035a73 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -102,6 +102,7 @@ (define_c_enum "unspec" [ UNSPEC_WREDUC_SUMU UNSPEC_WREDUC_SUM_ORDERED UNSPEC_WREDUC_SUM_UNORDERED + UNSPEC_SELECT_MASK ]) (define_c_enum "unspecv" [ diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 228d0f9a766..95451dc762b 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -6121,21 +6121,21 @@ (define_insn "@pred_not" (set_attr "vl_op_idx" "4") (set (attr "avl_type_idx") (const_int 5))]) -(define_insn "@pred_popcount" - [(set (match_operand:P 0 "register_operand" "=r") +(define_insn "@pred_popcount" + [(set (match_operand:P 0 "register_operand" "=r") (popcount:P - (unspec:VB - [(and:VB - (match_operand:VB 1 "vector_mask_operand" "vmWc1") - (match_operand:VB 2 "register_operand" " vr")) - (match_operand 3 "vector_length_operand" " rK") - (match_operand 4 "const_int_operand" " i") + (unspec:VB_VLS + [(and:VB_VLS + (match_operand:VB_VLS 1 "vector_mask_operand" "vmWc1") + (match_operand:VB_VLS 2 "register_operand" " vr")) + (match_operand 3 "vector_length_operand" " rK") + (match_operand 4 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))] "TARGET_VECTOR" "vcpop.m\t%0,%2%p1" [(set_attr "type" "vmpop") - (set_attr "mode" "")]) + (set_attr "mode" "")]) (define_insn "@pred_ffs" [(set (match_operand:P 0 "register_operand" "=r") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-1.c new file mode 100644 index 00000000000..f70979e81f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -fdump-tree-vect-details" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#define N 803 + +unsigned vect_a[N]; +unsigned vect_b[N]; + +/* +** test: +** ... +** vmsltu\.vv\s+v[0-9]+\s*,v[0-9]+,\s*v[0-9]+ +** vcpop\.m\s+[atx][0-9]+\s*,v[0-9]+ +** ... +*/ +unsigned test (unsigned x, int n) +{ + unsigned ret = 0; + + for (int i = 0; i < n; i++) + { + vect_b[i] = x + i; + + if (vect_a[i] > x) + break; + + vect_a[i] = x; + } + + return ret; +} + +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-2.c new file mode 100644 index 00000000000..d405783d2c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/early-break-2.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -fdump-tree-vect-details" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#define N 1728 + +unsigned vect_a[N]; +unsigned vect_b[N]; + +/* +** test: +** ... +** vmsltu\.vv\s+v[0-9]+\s*,v[0-9]+,\s*v[0-9]+ +** vcpop\.m\s+[atx][0-9]+\s*,v[0-9]+ +** ... +*/ +unsigned test (unsigned limit, int n) +{ + unsigned ret = 0; + + for (int i = 0; i < n; i++) + { + vect_b[i] = limit + i; + + if (vect_a[i] > limit) + { + ret = vect_b[i]; + return ret; + } + + vect_a[i] = limit; + } + + return ret; +} + +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 1 "vect" } } */