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Thu, 02 May 2024 11:59:32 -0700 (PDT) Received: from vineet-framework.ba.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id l3-20020a170902d04300b001ec83bdfe78sm1667287pll.63.2024.05.02.11.59.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 May 2024 11:59:31 -0700 (PDT) From: Vineet Gupta To: gcc-patches@gcc.gnu.org Cc: Jeff Law , kito.cheng@gmail.com, Palmer Dabbelt , Robin Dapp , gnu-toolchain@rivosinc.com, Vineet Gupta Subject: [PATCH 2/3] RISC-V: miscll comment fixes [NFC] Date: Thu, 2 May 2024 11:59:23 -0700 Message-Id: <20240502185924.2060196-3-vineetg@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502185924.2060196-1-vineetg@rivosinc.com> References: <20240502185924.2060196-1-vineetg@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org gcc/ChangeLog: * config/riscv/riscv.cc: Comment updates. * config/riscv/riscv.h: Ditto. Signed-off-by: Vineet Gupta --- gcc/config/riscv/riscv.cc | 6 ++++-- gcc/config/riscv/riscv.h | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 24d1ead3902c..79994a5ddf32 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1219,7 +1219,9 @@ riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) return riscv_const_insns (x) > 0; } -/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ +/* Implement TARGET_CANNOT_FORCE_CONST_MEM. + Return true if X cannot (or should not) be spilled to the + constant pool. */ static bool riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) @@ -8585,7 +8587,7 @@ riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2) && GET_MODE_CLASS (mode2) == MODE_FLOAT)); } -/* Implement CLASS_MAX_NREGS. */ +/* Implement TARGET_CLASS_MAX_NREGS. */ static unsigned char riscv_class_max_nregs (reg_class_t rclass, machine_mode mode) diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 7797e67317a6..58d0b09bf7d9 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -315,7 +315,7 @@ ASM_MISA_SPEC - FRAME_POINTER_REGNUM - 1 vl register - 1 vtype register - - 30 unused registers for future expansion + - 28 unused registers for future expansion - 32 vector registers */ #define FIRST_PSEUDO_REGISTER 128