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[2/3] RISC-V: miscll comment fixes [NFC]

Message ID 20240502185924.2060196-3-vineetg@rivosinc.com
State New
Headers show
Series Miscll fixlets | expand

Commit Message

Vineet Gupta May 2, 2024, 6:59 p.m. UTC 
gcc/ChangeLog:
	* config/riscv/riscv.cc: Comment updates.
	* config/riscv/riscv.h: Ditto.

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
---
 gcc/config/riscv/riscv.cc | 6 ++++--
 gcc/config/riscv/riscv.h  | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

Comments

Jeff Law May 2, 2024, 8:36 p.m. UTC | #1 
On 5/2/24 12:59 PM, Vineet Gupta wrote:
> gcc/ChangeLog:
> 	* config/riscv/riscv.cc: Comment updates.
> 	* config/riscv/riscv.h: Ditto.
OK
jeff
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Patch

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 24d1ead3902c..79994a5ddf32 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1219,7 +1219,9 @@  riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
   return riscv_const_insns (x) > 0;
 }
 
-/* Implement TARGET_CANNOT_FORCE_CONST_MEM.  */
+/* Implement TARGET_CANNOT_FORCE_CONST_MEM.
+   Return true if X cannot (or should not) be spilled to the
+   constant pool.  */
 
 static bool
 riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
@@ -8585,7 +8587,7 @@  riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2)
 	       && GET_MODE_CLASS (mode2) == MODE_FLOAT));
 }
 
-/* Implement CLASS_MAX_NREGS.  */
+/* Implement TARGET_CLASS_MAX_NREGS.  */
 
 static unsigned char
 riscv_class_max_nregs (reg_class_t rclass, machine_mode mode)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 7797e67317a6..58d0b09bf7d9 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -315,7 +315,7 @@  ASM_MISA_SPEC
 	- FRAME_POINTER_REGNUM
    - 1 vl register
    - 1 vtype register
-   - 30 unused registers for future expansion
+   - 28 unused registers for future expansion
    - 32 vector registers  */
 
 #define FIRST_PSEUDO_REGISTER 128