| Message ID | 20240214231521.1995779-2-quic_apinski@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Some minor internal optabs related fixes | expand |
On Thu, Feb 15, 2024 at 12:16 AM Andrew Pinski <quic_apinski@quicinc.com> wrote: > > Currently these use `@var{m3}` but the 3 here is a literal 3 > and not part of the mode itself so it should not be inside > the var. Fixed as such. > > Built the documentation to make sure it looks correct now. OK > gcc/ChangeLog: > > * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs, > smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the > var. > > Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com> > --- > gcc/doc/md.texi | 32 ++++++++++++++++---------------- > 1 file changed, 16 insertions(+), 16 deletions(-) > > diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi > index b0c61925120..274dd03d419 100644 > --- a/gcc/doc/md.texi > +++ b/gcc/doc/md.texi > @@ -5798,19 +5798,19 @@ is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode > equal or wider than the mode of the absolute difference. The result is placed > in operand 0, which is of the same mode as operand 3. > > -@cindex @code{widen_ssum@var{m3}} instruction pattern > -@cindex @code{widen_usum@var{m3}} instruction pattern > -@item @samp{widen_ssum@var{m3}} > -@itemx @samp{widen_usum@var{m3}} > +@cindex @code{widen_ssum@var{m}3} instruction pattern > +@cindex @code{widen_usum@var{m}3} instruction pattern > +@item @samp{widen_ssum@var{m}3} > +@itemx @samp{widen_usum@var{m}3} > Operands 0 and 2 are of the same mode, which is wider than the mode of > operand 1. Add operand 1 to operand 2 and place the widened result in > operand 0. (This is used express accumulation of elements into an accumulator > of a wider mode.) > > -@cindex @code{smulhs@var{m3}} instruction pattern > -@cindex @code{umulhs@var{m3}} instruction pattern > -@item @samp{smulhs@var{m3}} > -@itemx @samp{umulhs@var{m3}} > +@cindex @code{smulhs@var{m}3} instruction pattern > +@cindex @code{umulhs@var{m}3} instruction pattern > +@item @samp{smulhs@var{m}3} > +@itemx @samp{umulhs@var{m}3} > Signed/unsigned multiply high with scale. This is equivalent to the C code: > @smallexample > narrow op0, op1, op2; > @@ -5820,10 +5820,10 @@ op0 = (narrow) (((wide) op1 * (wide) op2) >> (N / 2 - 1)); > where the sign of @samp{narrow} determines whether this is a signed > or unsigned operation, and @var{N} is the size of @samp{wide} in bits. > > -@cindex @code{smulhrs@var{m3}} instruction pattern > -@cindex @code{umulhrs@var{m3}} instruction pattern > -@item @samp{smulhrs@var{m3}} > -@itemx @samp{umulhrs@var{m3}} > +@cindex @code{smulhrs@var{m}3} instruction pattern > +@cindex @code{umulhrs@var{m}3} instruction pattern > +@item @samp{smulhrs@var{m}3} > +@itemx @samp{umulhrs@var{m}3} > Signed/unsigned multiply high with round and scale. This is > equivalent to the C code: > @smallexample > @@ -5834,10 +5834,10 @@ op0 = (narrow) (((((wide) op1 * (wide) op2) >> (N / 2 - 2)) + 1) >> 1); > where the sign of @samp{narrow} determines whether this is a signed > or unsigned operation, and @var{N} is the size of @samp{wide} in bits. > > -@cindex @code{sdiv_pow2@var{m3}} instruction pattern > -@cindex @code{sdiv_pow2@var{m3}} instruction pattern > -@item @samp{sdiv_pow2@var{m3}} > -@itemx @samp{sdiv_pow2@var{m3}} > +@cindex @code{sdiv_pow2@var{m}3} instruction pattern > +@cindex @code{sdiv_pow2@var{m}3} instruction pattern > +@item @samp{sdiv_pow2@var{m}3} > +@itemx @samp{sdiv_pow2@var{m}3} > Signed division by power-of-2 immediate. Equivalent to: > @smallexample > signed op0, op1; > -- > 2.43.0 >
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index b0c61925120..274dd03d419 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -5798,19 +5798,19 @@ is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or wider than the mode of the absolute difference. The result is placed in operand 0, which is of the same mode as operand 3. -@cindex @code{widen_ssum@var{m3}} instruction pattern -@cindex @code{widen_usum@var{m3}} instruction pattern -@item @samp{widen_ssum@var{m3}} -@itemx @samp{widen_usum@var{m3}} +@cindex @code{widen_ssum@var{m}3} instruction pattern +@cindex @code{widen_usum@var{m}3} instruction pattern +@item @samp{widen_ssum@var{m}3} +@itemx @samp{widen_usum@var{m}3} Operands 0 and 2 are of the same mode, which is wider than the mode of operand 1. Add operand 1 to operand 2 and place the widened result in operand 0. (This is used express accumulation of elements into an accumulator of a wider mode.) -@cindex @code{smulhs@var{m3}} instruction pattern -@cindex @code{umulhs@var{m3}} instruction pattern -@item @samp{smulhs@var{m3}} -@itemx @samp{umulhs@var{m3}} +@cindex @code{smulhs@var{m}3} instruction pattern +@cindex @code{umulhs@var{m}3} instruction pattern +@item @samp{smulhs@var{m}3} +@itemx @samp{umulhs@var{m}3} Signed/unsigned multiply high with scale. This is equivalent to the C code: @smallexample narrow op0, op1, op2; @@ -5820,10 +5820,10 @@ op0 = (narrow) (((wide) op1 * (wide) op2) >> (N / 2 - 1)); where the sign of @samp{narrow} determines whether this is a signed or unsigned operation, and @var{N} is the size of @samp{wide} in bits. -@cindex @code{smulhrs@var{m3}} instruction pattern -@cindex @code{umulhrs@var{m3}} instruction pattern -@item @samp{smulhrs@var{m3}} -@itemx @samp{umulhrs@var{m3}} +@cindex @code{smulhrs@var{m}3} instruction pattern +@cindex @code{umulhrs@var{m}3} instruction pattern +@item @samp{smulhrs@var{m}3} +@itemx @samp{umulhrs@var{m}3} Signed/unsigned multiply high with round and scale. This is equivalent to the C code: @smallexample @@ -5834,10 +5834,10 @@ op0 = (narrow) (((((wide) op1 * (wide) op2) >> (N / 2 - 2)) + 1) >> 1); where the sign of @samp{narrow} determines whether this is a signed or unsigned operation, and @var{N} is the size of @samp{wide} in bits. -@cindex @code{sdiv_pow2@var{m3}} instruction pattern -@cindex @code{sdiv_pow2@var{m3}} instruction pattern -@item @samp{sdiv_pow2@var{m3}} -@itemx @samp{sdiv_pow2@var{m3}} +@cindex @code{sdiv_pow2@var{m}3} instruction pattern +@cindex @code{sdiv_pow2@var{m}3} instruction pattern +@item @samp{sdiv_pow2@var{m}3} +@itemx @samp{sdiv_pow2@var{m}3} Signed division by power-of-2 immediate. Equivalent to: @smallexample signed op0, op1;
Currently these use `@var{m3}` but the 3 here is a literal 3 and not part of the mode itself so it should not be inside the var. Fixed as such. Built the documentation to make sure it looks correct now. gcc/ChangeLog: * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs, smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the var. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com> --- gcc/doc/md.texi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-)