From patchwork Tue Feb 6 09:17:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yulong X-Patchwork-Id: 1895560 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TTd2z1wSLz23gT for ; Tue, 6 Feb 2024 20:18:35 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3236C3858D33 for ; Tue, 6 Feb 2024 09:18:33 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTPS id C37A83858C2A for ; Tue, 6 Feb 2024 09:18:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C37A83858C2A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C37A83858C2A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707211092; cv=none; b=TsiEkvbAd+++FJLcisJpvKA9BUOan+f7BTQDRzn7konmSUwFB1Ngla8Rn4DPB5UQnp2dvy7G9jIdG7L4xG1cOKXVnbui7xXRV/9Y7dzbeYAAvrcqBbKzBIhAHnzhgyVhT6LxyGLjTonK3QTEiA2m3qtLaFIKDpB+Na0PDSomGeI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707211092; c=relaxed/simple; bh=SCfqlin7NxdxIUSZA3OiDVrDwSACOawdNK3PKYp64g0=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=B3ic47ci3jFIxBPhzuFCtzEO5jGc1CZ1iLjddN8Mzjpea6951yKSq8uyN03i5PwfmsSPVNAPtQvw5kOM6bSMTLFeUT6p0OH7d3sxPdHhPqdSojwBPQXWY93iY6YVRjwO6JZPTe1GOkBg9Iy88xCSkBK3IdlXVGiOvDr5KNAk6wU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [122.8.183.87]) by APP-01 (Coremail) with SMTP id qwCowAD3_Z1C+cFlmSUfAQ--.4626S2; Tue, 06 Feb 2024 17:17:57 +0800 (CST) From: shiyulong@iscas.ac.cn To: gcc-patches@gcc.gnu.org Cc: palmer@dabbelt.com, kito.cheng@sifive.com, wuwei2016@iscas.ac.cn, jiawei@iscas.ac.cn, shihua@iscas.ac.cn, chenyixuan@iscas.ac.cn, dje.gcc@gmail.com, mirimmad@outlook.com, yulong Subject: [PATCH V1] RISC-V: Add mininal support for zabha extension. Date: Tue, 6 Feb 2024 17:17:47 +0800 Message-Id: <20240206091747.3310811-1-shiyulong@iscas.ac.cn> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CM-TRANSID: qwCowAD3_Z1C+cFlmSUfAQ--.4626S2 X-Coremail-Antispam: 1UD129KBjvJXoWxtw18uw4fAr48uF48KrW3Jrb_yoWfCFy3pr WUGw47Ary5ZrZag34IkFWjqw15CwnrKF4jvF98W390kryUWw1kJ3y0kry2qa4UAF1Fqw15 Aa1xWw1Uu3y5Kw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9v14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkIecxEwVAFwVW8uwCF04k20xvY0x0EwIxGrwCFx2 IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v2 6r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67 AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IY s7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr 0_GrUvcSsGvfC2KfnxnUUI43ZEXa7VUbxR67UUUUU== X-Originating-IP: [122.8.183.87] X-CM-SenderInfo: 5vkl53porqwq5lvft2wodfhubq/ X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_LOW, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: yulong This patch add the mininal support for zabha extension. The doc url as follow: https://github.com/riscv/riscv-zabha/blob/v1.0-rc1/zabha.adoc There are have no amocas.[b|h] instructions, because the zacas extension is not merged. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zabha extension name. * config/riscv/riscv.md (amo_addqi3): New mode. (amo_addhi3): Ditto. (amo_minqi3): Ditto. (amo_minuqi3): Ditto. (amo_minhi3): Ditto. (amo_minuhi3): Ditto. (amo_maxqi3): Ditto. (amo_maxuqi3): Ditto. (amo_maxhi3): Ditto. (amo_maxuhi3): Ditto. (amo_andqi3): Ditto. (amo_andhi3): Ditto. (amo_orqi3): Ditto. (amo_orhi3): Ditto. (amo_xorqi3): Ditto. (amo_xorhi3): Ditto. (amo_swapqi3): Ditto. (amo_swaphi3): Ditto. * config/riscv/riscv.opt: Add zabha extension. --- gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/riscv.md | 167 ++++++++++++++++++++++++ gcc/config/riscv/riscv.opt | 2 + 3 files changed, 171 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 631ce8309a0..9c3be0d7651 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -250,6 +250,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"za64rs", ISA_SPEC_CLASS_NONE, 1, 0}, {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0}, {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zabha", ISA_SPEC_CLASS_NONE, 1, 0}, {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1504,6 +1505,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS}, {"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS}, {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, + {"zabha", &gcc_options::x_riscv_za_subext, MASK_ZABHA}, {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA}, {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB}, diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 39b29795cd6..058b63ac7f0 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -134,6 +134,9 @@ ;; XTheadInt unspec UNSPECV_XTHEADINT_PUSH UNSPECV_XTHEADINT_POP + + ;; Zabha instructions. + UNSPEC_AMO_SWAP ]) (define_constants @@ -849,6 +852,24 @@ [(set_attr "type" "arith") (set_attr "mode" "SI")]) +(define_insn "amo_addqi3" + [(set (match_operand:QI 0 "register_operand" "=r,r") + (plus:QI (match_operand:QI 1 "register_operand" " r,r") + (match_operand:QI 2 "arith_operand" " r,r")))] + "TARGET_ZABHA" + "amoadd.b\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "QI")]) + +(define_insn "amo_addhi3" + [(set (match_operand:HI 0 "register_operand" "=r,r") + (plus:HI (match_operand:HI 1 "register_operand" " r,r") + (match_operand:HI 2 "arith_operand" " r,r")))] + "TARGET_ZABHA" + "amoadd.h\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "HI")]) + ;; ;; .................... ;; @@ -1645,6 +1666,78 @@ [(set_attr "type" "fmove") (set_attr "mode" "")]) +(define_insn "amo_minqi3" + [(set (match_operand:QI 0 "register_operand" "=r") + (smin:QI (match_operand:QI 1 "register_operand" " r") + (match_operand:QI 2 "register_operand" " r")))] + "TARGET_ZABHA" + "amomin.b\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "QI")]) + +(define_insn "amo_minuqi3" + [(set (match_operand:QI 0 "register_operand" "=r") + (umin:QI (match_operand:QI 1 "register_operand" " r") + (match_operand:QI 2 "register_operand" " r")))] + "TARGET_ZABHA" + "amominu.b\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "QI")]) + +(define_insn "amo_minhi3" + [(set (match_operand:HI 0 "register_operand" "=r") + (smin:HI (match_operand:HI 1 "register_operand" " r") + (match_operand:HI 2 "register_operand" " r")))] + "TARGET_ZABHA" + "amomin.h\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "HI")]) + +(define_insn "amo_minuhi3" + [(set (match_operand:HI 0 "register_operand" "=r") + (umin:HI (match_operand:HI 1 "register_operand" " r") + (match_operand:HI 2 "register_operand" " r")))] + "TARGET_ZABHA" + "amominu.h\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "HI")]) + +(define_insn "amo_maxqi3" + [(set (match_operand:QI 0 "register_operand" "=r") + (smax:QI (match_operand:QI 1 "register_operand" " r") + (match_operand:QI 2 "register_operand" " r")))] + "TARGET_ZABHA" + "amomax.b\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "QI")]) + +(define_insn "amo_maxuqi3" + [(set (match_operand:QI 0 "register_operand" "=r") + (umax:QI (match_operand:QI 1 "register_operand" " r") + (match_operand:QI 2 "register_operand" " r")))] + "TARGET_ZABHA" + "amomaxu.b\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "QI")]) + +(define_insn "amo_maxhi3" + [(set (match_operand:HI 0 "register_operand" "=r") + (smax:HI (match_operand:HI 1 "register_operand" " r") + (match_operand:HI 2 "register_operand" " r")))] + "TARGET_ZABHA" + "amomax.h\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "HI")]) + +(define_insn "amo_maxuhi3" + [(set (match_operand:HI 0 "register_operand" "=r") + (umax:HI (match_operand:HI 1 "register_operand" " r") + (match_operand:HI 2 "register_operand" " r")))] + "TARGET_ZABHA" + "amomaxu.h\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "HI")]) + ;; ;; .................... ;; @@ -1690,6 +1783,24 @@ [(set_attr "type" "logical") (set_attr "mode" "")]) +(define_insn "amo_andqi3" + [(set (match_operand:QI 0 "register_operand" "=r,r") + (and:QI (match_operand:QI 1 "register_operand" "r,r") + (match_operand:QI 2 "arith_operand" " r,r")))] + "TARGET_ZABHA" + "amoand.b\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "QI")]) + +(define_insn "amo_andhi3" + [(set (match_operand:HI 0 "register_operand" "=r,r") + (and:HI (match_operand:HI 1 "register_operand" "r,r") + (match_operand:HI 2 "arith_operand" " r,r")))] + "TARGET_ZABHA" + "amoand.h\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "HI")]) + (define_insn "3" [(set (match_operand:X 0 "register_operand" "=r,r") (any_or:X (match_operand:X 1 "register_operand" "%r,r") @@ -1724,6 +1835,42 @@ [(set_attr "type" "logical") (set_attr "mode" "SI")]) +(define_insn "amo_orqi3" + [(set (match_operand:QI 0 "register_operand" "=r,r") + (ior:QI (match_operand:QI 1 "register_operand" " r,r") + (match_operand:QI 2 "arith_operand" " r,r")))] + "TARGET_ZABHA" + "amoor.b\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "QI")]) + +(define_insn "amo_orhi3" + [(set (match_operand:HI 0 "register_operand" "=r,r") + (ior:HI (match_operand:HI 1 "register_operand" " r,r") + (match_operand:HI 2 "arith_operand" " r,r")))] + "TARGET_ZABHA" + "amoor.h\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "HI")]) + +(define_insn "amo_xorqi3" + [(set (match_operand:QI 0 "register_operand" "=r,r") + (xor:QI (match_operand:QI 1 "register_operand" " r,r") + (match_operand:QI 2 "arith_operand" " r,r")))] + "TARGET_ZABHA" + "amoxor.b\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "QI")]) + +(define_insn "amo_xorhi3" + [(set (match_operand:HI 0 "register_operand" "=r,r") + (xor:HI (match_operand:HI 1 "register_operand" " r,r") + (match_operand:HI 2 "arith_operand" " r,r")))] + "TARGET_ZABHA" + "amoxor.h\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "HI")]) + ;; ;; .................... ;; @@ -3841,6 +3988,26 @@ [(set_attr "type" "load") (set (attr "length") (const_int 8))]) +(define_insn "amo_swapqi3" + [(set (match_operand:QI 0 "register_operand" "=r") + (unspec:QI [(match_operand:QI 1 "register_operand" "r") + (match_operand:QI 2 "register_operand" "r")] + UNSPEC_AMO_SWAP))] + "TARGET_ZABHA" + "amoswap.b\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "QI")]) + +(define_insn "amo_swaphi3" + [(set (match_operand:HI 0 "register_operand" "=r") + (unspec:HI [(match_operand:HI 1 "register_operand" "r") + (match_operand:HI 2 "register_operand" "r")] + UNSPEC_AMO_SWAP))] + "TARGET_ZABHA" + "amoswap.h\t%0,%1,%2" + [(set_attr "type" "atomic") + (set_attr "mode" "HI")]) + (include "bitmanip.md") (include "crypto.md") (include "sync.md") diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index f6ff70b2b30..1136a5301ea 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -244,6 +244,8 @@ Mask(ZA64RS) Var(riscv_za_subext) Mask(ZA128RS) Var(riscv_za_subext) +Mask(ZABHA) Var(riscv_za_subext) + TargetVariable int riscv_zb_subext