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(unknown [IPv6:240e:358:11d0:200:dc73:854d:832e:8]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 0760866BE1; Sun, 4 Feb 2024 13:01:26 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: YunQiang Su , Jeff Law , Xi Ruoyao Subject: [PATCH] MIPS: Fix wrong MSA FP vector negation Date: Mon, 5 Feb 2024 02:00:37 +0800 Message-ID: <20240204180106.468674-1-xry111@xry111.site> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is wrong because -0.0 is not 0 - 0.0. This causes some Python tests to fail when Python is built with MSA enabled. Use the bnegi.df instructions to simply reverse the sign bit instead. gcc/ChangeLog: * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr. (neg2): Change the mode iterator from MSA to IMSA because in FP arithmetic we cannot use (0 - x) for -x. (neg2): New define_insn to implement FP vector negation, using a bnegi instruction to negate the sign bit. --- Bootstrapped and regtested on mips64el-linux-gnuabi64. Ok for trunk and/or release branches? gcc/config/mips/mips-msa.md | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md index 83d9a08e360..920161ed1d8 100644 --- a/gcc/config/mips/mips-msa.md +++ b/gcc/config/mips/mips-msa.md @@ -231,6 +231,10 @@ (define_mode_attr bitimm (V4SI "uimm5") (V2DI "uimm6")]) +;; The index of sign bit in FP vector elements. +(define_mode_attr elmsgnbit [(V2DF "63") (V4DF "63") + (V4SF "31") (V8SF "31")]) + (define_expand "vec_init" [(match_operand:MSA 0 "register_operand") (match_operand:MSA 1 "")] @@ -597,9 +601,9 @@ (define_expand "abs2" }) (define_expand "neg2" - [(set (match_operand:MSA 0 "register_operand") - (minus:MSA (match_dup 2) - (match_operand:MSA 1 "register_operand")))] + [(set (match_operand:IMSA 0 "register_operand") + (minus:IMSA (match_dup 2) + (match_operand:IMSA 1 "register_operand")))] "ISA_HAS_MSA" { rtx reg = gen_reg_rtx (mode); @@ -607,6 +611,14 @@ (define_expand "neg2" operands[2] = reg; }) +(define_insn "neg2" + [(set (match_operand:FMSA 0 "register_operand" "=f") + (neg (match_operand:FMSA 1 "register_operand" "f")))] + "ISA_HAS_MSA" + "bnegi.\t%w0,%w1," + [(set_attr "type" "simd_bit") + (set_attr "mode" "")]) + (define_expand "msa_ldi" [(match_operand:IMSA 0 "register_operand") (match_operand 1 "const_imm10_operand")]