[v2] RISC-V: Add minimal support for 7 new unprivileged extensions

The RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions

These extensions don't add any new features but
describe existing features. So this patch only adds parsing.

Za64rs: Reservation set size of 64 bytes
Za128rs: Reservation set size of 128 bytes
Ziccif: Main memory supports instruction fetch with atomicity requirement
Ziccrse: Main memory supports forward progress on LR/SC sequences
Ziccamoa: Main memory supports all atomics in A
Zicclsm: Main memory supports misaligned loads/stores
Zic64b: Cache block size isf 64 bytes

gcc/ChangeLog:

	* config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
	Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
	* config/riscv/riscv.opt: New macro for 7 new unprivileged
	extensions.
	* doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
	Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
gcc/testsuite/ChangeLog:

	* gcc.target/riscv/za-ext.c: New test.
	* gcc.target/riscv/zi-ext.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc | 14 ++++++++++++
 gcc/config/riscv/riscv.opt              | 14 ++++++++++++
 gcc/doc/invoke.texi                     | 28 ++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/za-ext.c | 17 +++++++++++++++
 gcc/testsuite/gcc.target/riscv/zi-ext.c | 29 +++++++++++++++++++++++++
 5 files changed, 102 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/za-ext.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zi-ext.c

Pushed to trunk, thanks :)

On Thu, Feb 1, 2024 at 5:16 PM Monk Chiang <monk.chiang@sifive.com> wrote:
>
> The RISC-V Profiles specification here:
> https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
>
> These extensions don't add any new features but
> describe existing features. So this patch only adds parsing.
>
> Za64rs: Reservation set size of 64 bytes
> Za128rs: Reservation set size of 128 bytes
> Ziccif: Main memory supports instruction fetch with atomicity requirement
> Ziccrse: Main memory supports forward progress on LR/SC sequences
> Ziccamoa: Main memory supports all atomics in A
> Zicclsm: Main memory supports misaligned loads/stores
> Zic64b: Cache block size isf 64 bytes
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
>         Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
>         * config/riscv/riscv.opt: New macro for 7 new unprivileged
>         extensions.
>         * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
>         Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/za-ext.c: New test.
>         * gcc.target/riscv/zi-ext.c: New test.
> ---
>  gcc/common/config/riscv/riscv-common.cc | 14 ++++++++++++
>  gcc/config/riscv/riscv.opt              | 14 ++++++++++++
>  gcc/doc/invoke.texi                     | 28 ++++++++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/za-ext.c | 17 +++++++++++++++
>  gcc/testsuite/gcc.target/riscv/zi-ext.c | 29 +++++++++++++++++++++++++
>  5 files changed, 102 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/za-ext.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zi-ext.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 6ac0422ac13..631ce8309a0 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -247,6 +247,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>
>    {"zicond", ISA_SPEC_CLASS_NONE, 1, 0},
>
> +  {"za64rs",  ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
>    {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
>
>    {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -276,6 +278,11 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>    {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
>    {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
>    {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zic64b",   ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"ziccamoa", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"ziccif",   ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zicclsm",  ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"ziccrse",  ISA_SPEC_CLASS_NONE, 1, 0},
>
>    {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
>    {"zihpm",  ISA_SPEC_CLASS_NONE, 2, 0},
> @@ -1494,6 +1501,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>    {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
>    {"zicond",   &gcc_options::x_riscv_zi_subext, MASK_ZICOND},
>
> +  {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS},
> +  {"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS},
>    {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
>
>    {"zba",    &gcc_options::x_riscv_zb_subext, MASK_ZBA},
> @@ -1523,6 +1532,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>    {"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ},
>    {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM},
>    {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP},
> +  {"zic64b", &gcc_options::x_riscv_zicmo_subext, MASK_ZIC64B},
> +  {"ziccamoa", &gcc_options::x_riscv_zicmo_subext, MASK_ZICCAMOA},
> +  {"ziccif", &gcc_options::x_riscv_zicmo_subext, MASK_ZICCIF},
> +  {"zicclsm", &gcc_options::x_riscv_zicmo_subext, MASK_ZICCLSM},
> +  {"ziccrse", &gcc_options::x_riscv_zicmo_subext, MASK_ZICCRSE},
>
>    {"zve32x",   &gcc_options::x_target_flags, MASK_VECTOR},
>    {"zve32f",   &gcc_options::x_target_flags, MASK_VECTOR},
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index b6d8e9a3f74..f6ff70b2b30 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -225,11 +225,25 @@ Mask(ZIHINTPAUSE) Var(riscv_zi_subext)
>
>  Mask(ZICOND)      Var(riscv_zi_subext)
>
> +Mask(ZIC64B)      Var(riscv_zi_subext)
> +
> +Mask(ZICCAMOA)    Var(riscv_zi_subext)
> +
> +Mask(ZICCIF)      Var(riscv_zi_subext)
> +
> +Mask(ZICCLSM)     Var(riscv_zi_subext)
> +
> +Mask(ZICCRSE)     Var(riscv_zi_subext)
> +
>  TargetVariable
>  int riscv_za_subext
>
>  Mask(ZAWRS) Var(riscv_za_subext)
>
> +Mask(ZA64RS)  Var(riscv_za_subext)
> +
> +Mask(ZA128RS) Var(riscv_za_subext)
> +
>  TargetVariable
>  int riscv_zb_subext
>
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index ca2c0e90452..09abd2aef31 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -30262,6 +30262,14 @@ Supported extension are listed below:
>  @tab 1.0
>  @tab Integer conditional operations extension.
>
> +@item za64rs
> +@tab 1.0
> +@tab Reservation set size of 64 bytes.
> +
> +@item za128rs
> +@tab 1.0
> +@tab Reservation set size of 128 bytes.
> +
>  @item zawrs
>  @tab 1.0
>  @tab Wait-on-reservation-set extension.
> @@ -30370,6 +30378,26 @@ Supported extension are listed below:
>  @tab 1.0
>  @tab Cache-block prefetch extension.
>
> +@item zic64b
> +@tab 1.0
> +@tab Cache block size isf 64 bytes.
> +
> +@item ziccamoa
> +@tab 1.0
> +@tab Main memory supports all atomics in A.
> +
> +@item ziccif
> +@tab 1.0
> +@tab Main memory supports instruction fetch with atomicity requirement.
> +
> +@item zicclsm
> +@tab 1.0
> +@tab Main memory supports misaligned loads/stores.
> +
> +@item ziccrse
> +@tab 1.0
> +@tab Main memory supports forward progress on LR/SC sequences.
> +
>  @item zicntr
>  @tab 2.0
>  @tab Standard extension for base counters and timers.
> diff --git a/gcc/testsuite/gcc.target/riscv/za-ext.c b/gcc/testsuite/gcc.target/riscv/za-ext.c
> new file mode 100644
> index 00000000000..126da2fcadd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/za-ext.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_za64rs_za128rs" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_za64rs_za128rs" { target { rv32 } } } */
> +
> +#ifndef __riscv_za64rs
> +#error "Feature macro for 'za64rs' not defined"
> +#endif
> +
> +#ifndef __riscv_za128rs
> +#error "Feature macro for 'za128rs' not defined"
> +#endif
> +
> +int
> +foo (int a)
> +{
> +  return a;
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/zi-ext.c b/gcc/testsuite/gcc.target/riscv/zi-ext.c
> new file mode 100644
> index 00000000000..65a7acb32af
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zi-ext.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_zic64b_ziccamoa_ziccif_zicclsm_ziccrse" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zic64b_ziccamoa_ziccif_zicclsm_ziccrse" { target { rv32 } } } */
> +
> +#ifndef __riscv_zic64b
> +#error "Feature macro for 'zic64b' not defined"
> +#endif
> +
> +#ifndef __riscv_ziccamoa
> +#error "Feature macro for 'ziccamoa' not defined"
> +#endif
> +
> +#ifndef __riscv_ziccif
> +#error "Feature macro for 'ziccif' not defined"
> +#endif
> +
> +#ifndef __riscv_zicclsm
> +#error "Feature macro for 'zicclsm' not defined"
> +#endif
> +
> +#ifndef __riscv_ziccrse
> +#error "Feature macro for 'ziccrse' not defined"
> +#endif
> +
> +int
> +foo (int a)
> +{
> +  return a;
> +}
> --
> 2.40.1
>