diff mbox series

Loongarch: Remove vec_concatz<mode> pattern

Message ID 20240124091913.38156-1-xujiahao@loongson.cn
State New
Headers show
Series Loongarch: Remove vec_concatz<mode> pattern | expand

Commit Message

Jiahao Xu Jan. 24, 2024, 9:19 a.m. UTC 
It is incorrect to use vld/vori to implement the vec_concatz<mode> because when the LSX
instruction is used to update the value of the vector register, the upper 128 bits of
the vector register will not be zeroed.

gcc/ChangeLog:

	* config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
	* config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.

Comments

Lulu Cheng Jan. 25, 2024, 7:46 a.m. UTC | #1 
Jiahao:

  Note that the LoongArch 'a' in the title needs to be capitalized.

  I modified this patch and incorporated it first.


在 2024/1/24 下午5:19, Jiahao Xu 写道:
> It is incorrect to use vld/vori to implement the vec_concatz<mode> because when the LSX
> instruction is used to update the value of the vector register, the upper 128 bits of
> the vector register will not be zeroed.
>
> gcc/ChangeLog:
>
> 	* config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
> 	* config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
>
> diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
> index 90f66ee4d24..e2115ffb884 100644
> --- a/gcc/config/loongarch/lasx.md
> +++ b/gcc/config/loongarch/lasx.md
> @@ -582,21 +582,6 @@ (define_insn "lasx_xvinsgr2vr_<lasxfmt_f_wd>"
>     [(set_attr "type" "simd_insert")
>      (set_attr "mode" "<MODE>")])
>   
> -(define_insn "@vec_concatz<mode>"
> -  [(set (match_operand:LASX 0 "register_operand" "=f")
> -    (vec_concat:LASX
> -      (match_operand:<VHMODE256_ALL> 1 "nonimmediate_operand")
> -      (match_operand:<VHMODE256_ALL> 2 "const_0_operand")))]
> -  "ISA_HAS_LASX"
> -{
> -  if (MEM_P (operands[1]))
> -    return "vld\t%w0,%1";
> -  else
> -    return "vori.b\t%w0,%w1,0";
> -}
> -  [(set_attr "type" "simd_splat")
> -   (set_attr "mode" "<MODE>")])
> -
>   (define_insn "vec_concat<mode>"
>     [(set (match_operand:LASX 0 "register_operand" "=f")
>   	(vec_concat:LASX
> diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
> index 072c68d97e3..cd335827570 100644
> --- a/gcc/config/loongarch/loongarch.cc
> +++ b/gcc/config/loongarch/loongarch.cc
> @@ -9917,17 +9917,12 @@ loongarch_expand_vector_group_init (rtx target, rtx vals)
>         gcc_unreachable ();
>       }
>   
> -  if (high == CONST0_RTX (half_mode))
> -    emit_insn (gen_vec_concatz (vmode, target, low, high));
> -  else
> -    {
> -      if (!register_operand (low, half_mode))
> -	low = force_reg (half_mode, low);
> -      if (!register_operand (high, half_mode))
> -	high = force_reg (half_mode, high);
> -      emit_insn (gen_rtx_SET (target,
> -			      gen_rtx_VEC_CONCAT (vmode, low, high)));
> -    }
> +  if (!register_operand (low, half_mode))
> +    low = force_reg (half_mode, low);
> +  if (!register_operand (high, half_mode))
> +    high = force_reg (half_mode, high);
> +  emit_insn (gen_rtx_SET (target,
> +			  gen_rtx_VEC_CONCAT (vmode, low, high)));
>   }
>   
>   /* Expand initialization of a vector which has all same elements.  */
Jiahao Xu Jan. 25, 2024, 7:50 a.m. UTC | #2 
在 2024/1/25 下午3:46, chenglulu 写道:
> Jiahao:
>
>  Note that the LoongArch 'a' in the title needs to be capitalized.
>
>  I modified this patch and incorporated it first.
>
>
Thanks, I'll pay attention next time.
> 在 2024/1/24 下午5:19, Jiahao Xu 写道:
>> It is incorrect to use vld/vori to implement the vec_concatz<mode> 
>> because when the LSX
>> instruction is used to update the value of the vector register, the 
>> upper 128 bits of
>> the vector register will not be zeroed.
>>
>> gcc/ChangeLog:
>>
>>     * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this 
>> define_insn pattern.
>>     * config/loongarch/loongarch.cc 
>> (loongarch_expand_vector_group_init): Use vec_concat<mode>.
>>
>> diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
>> index 90f66ee4d24..e2115ffb884 100644
>> --- a/gcc/config/loongarch/lasx.md
>> +++ b/gcc/config/loongarch/lasx.md
>> @@ -582,21 +582,6 @@ (define_insn "lasx_xvinsgr2vr_<lasxfmt_f_wd>"
>>     [(set_attr "type" "simd_insert")
>>      (set_attr "mode" "<MODE>")])
>>   -(define_insn "@vec_concatz<mode>"
>> -  [(set (match_operand:LASX 0 "register_operand" "=f")
>> -    (vec_concat:LASX
>> -      (match_operand:<VHMODE256_ALL> 1 "nonimmediate_operand")
>> -      (match_operand:<VHMODE256_ALL> 2 "const_0_operand")))]
>> -  "ISA_HAS_LASX"
>> -{
>> -  if (MEM_P (operands[1]))
>> -    return "vld\t%w0,%1";
>> -  else
>> -    return "vori.b\t%w0,%w1,0";
>> -}
>> -  [(set_attr "type" "simd_splat")
>> -   (set_attr "mode" "<MODE>")])
>> -
>>   (define_insn "vec_concat<mode>"
>>     [(set (match_operand:LASX 0 "register_operand" "=f")
>>       (vec_concat:LASX
>> diff --git a/gcc/config/loongarch/loongarch.cc 
>> b/gcc/config/loongarch/loongarch.cc
>> index 072c68d97e3..cd335827570 100644
>> --- a/gcc/config/loongarch/loongarch.cc
>> +++ b/gcc/config/loongarch/loongarch.cc
>> @@ -9917,17 +9917,12 @@ loongarch_expand_vector_group_init (rtx 
>> target, rtx vals)
>>         gcc_unreachable ();
>>       }
>>   -  if (high == CONST0_RTX (half_mode))
>> -    emit_insn (gen_vec_concatz (vmode, target, low, high));
>> -  else
>> -    {
>> -      if (!register_operand (low, half_mode))
>> -    low = force_reg (half_mode, low);
>> -      if (!register_operand (high, half_mode))
>> -    high = force_reg (half_mode, high);
>> -      emit_insn (gen_rtx_SET (target,
>> -                  gen_rtx_VEC_CONCAT (vmode, low, high)));
>> -    }
>> +  if (!register_operand (low, half_mode))
>> +    low = force_reg (half_mode, low);
>> +  if (!register_operand (high, half_mode))
>> +    high = force_reg (half_mode, high);
>> +  emit_insn (gen_rtx_SET (target,
>> +              gen_rtx_VEC_CONCAT (vmode, low, high)));
>>   }
>>     /* Expand initialization of a vector which has all same 
>> elements.  */
Lulu Cheng Jan. 25, 2024, 7:55 a.m. UTC | #3 
Pushed to r14-8414.

在 2024/1/24 下午5:19, Jiahao Xu 写道:
> It is incorrect to use vld/vori to implement the vec_concatz<mode> because when the LSX
> instruction is used to update the value of the vector register, the upper 128 bits of
> the vector register will not be zeroed.
>
> gcc/ChangeLog:
>
> 	* config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
> 	* config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
>
> diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
> index 90f66ee4d24..e2115ffb884 100644
> --- a/gcc/config/loongarch/lasx.md
> +++ b/gcc/config/loongarch/lasx.md
> @@ -582,21 +582,6 @@ (define_insn "lasx_xvinsgr2vr_<lasxfmt_f_wd>"
>     [(set_attr "type" "simd_insert")
>      (set_attr "mode" "<MODE>")])
>   
> -(define_insn "@vec_concatz<mode>"
> -  [(set (match_operand:LASX 0 "register_operand" "=f")
> -    (vec_concat:LASX
> -      (match_operand:<VHMODE256_ALL> 1 "nonimmediate_operand")
> -      (match_operand:<VHMODE256_ALL> 2 "const_0_operand")))]
> -  "ISA_HAS_LASX"
> -{
> -  if (MEM_P (operands[1]))
> -    return "vld\t%w0,%1";
> -  else
> -    return "vori.b\t%w0,%w1,0";
> -}
> -  [(set_attr "type" "simd_splat")
> -   (set_attr "mode" "<MODE>")])
> -
>   (define_insn "vec_concat<mode>"
>     [(set (match_operand:LASX 0 "register_operand" "=f")
>   	(vec_concat:LASX
> diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
> index 072c68d97e3..cd335827570 100644
> --- a/gcc/config/loongarch/loongarch.cc
> +++ b/gcc/config/loongarch/loongarch.cc
> @@ -9917,17 +9917,12 @@ loongarch_expand_vector_group_init (rtx target, rtx vals)
>         gcc_unreachable ();
>       }
>   
> -  if (high == CONST0_RTX (half_mode))
> -    emit_insn (gen_vec_concatz (vmode, target, low, high));
> -  else
> -    {
> -      if (!register_operand (low, half_mode))
> -	low = force_reg (half_mode, low);
> -      if (!register_operand (high, half_mode))
> -	high = force_reg (half_mode, high);
> -      emit_insn (gen_rtx_SET (target,
> -			      gen_rtx_VEC_CONCAT (vmode, low, high)));
> -    }
> +  if (!register_operand (low, half_mode))
> +    low = force_reg (half_mode, low);
> +  if (!register_operand (high, half_mode))
> +    high = force_reg (half_mode, high);
> +  emit_insn (gen_rtx_SET (target,
> +			  gen_rtx_VEC_CONCAT (vmode, low, high)));
>   }
>   
>   /* Expand initialization of a vector which has all same elements.  */
diff mbox series

Patch

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 90f66ee4d24..e2115ffb884 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -582,21 +582,6 @@  (define_insn "lasx_xvinsgr2vr_<lasxfmt_f_wd>"
   [(set_attr "type" "simd_insert")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "@vec_concatz<mode>"
-  [(set (match_operand:LASX 0 "register_operand" "=f")
-    (vec_concat:LASX
-      (match_operand:<VHMODE256_ALL> 1 "nonimmediate_operand")
-      (match_operand:<VHMODE256_ALL> 2 "const_0_operand")))]
-  "ISA_HAS_LASX"
-{
-  if (MEM_P (operands[1]))
-    return "vld\t%w0,%1";
-  else
-    return "vori.b\t%w0,%w1,0";
-}
-  [(set_attr "type" "simd_splat")
-   (set_attr "mode" "<MODE>")])
-
 (define_insn "vec_concat<mode>"
   [(set (match_operand:LASX 0 "register_operand" "=f")
 	(vec_concat:LASX
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 072c68d97e3..cd335827570 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -9917,17 +9917,12 @@  loongarch_expand_vector_group_init (rtx target, rtx vals)
       gcc_unreachable ();
     }
 
-  if (high == CONST0_RTX (half_mode))
-    emit_insn (gen_vec_concatz (vmode, target, low, high));
-  else
-    {
-      if (!register_operand (low, half_mode))
-	low = force_reg (half_mode, low);
-      if (!register_operand (high, half_mode))
-	high = force_reg (half_mode, high);
-      emit_insn (gen_rtx_SET (target,
-			      gen_rtx_VEC_CONCAT (vmode, low, high)));
-    }
+  if (!register_operand (low, half_mode))
+    low = force_reg (half_mode, low);
+  if (!register_operand (high, half_mode))
+    high = force_reg (half_mode, high);
+  emit_insn (gen_rtx_SET (target,
+			  gen_rtx_VEC_CONCAT (vmode, low, high)));
 }
 
 /* Expand initialization of a vector which has all same elements.  */