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envelope-from=yangyujie@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org gcc/ChangeLog: * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution variable with the common la_ prefix. * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution flags as saved using TargetVariable. * config/loongarch/loongarch.opt: Same. * config/loongarch/loongarch-def.h: Define evolution_set to mark changes to the -march default. * config/loongarch/loongarch-driver.cc: Same. * config/loongarch/loongarch-opts.cc: Same. * config/loongarch/loongarch-opts.h: Define and use ISA evolution conditions around the la_target structure. * config/loongarch/loongarch.cc: Same. * config/loongarch/loongarch.md: Same. * config/loongarch/loongarch-builtins.cc: Same. * config/loongarch/loongarch-c.cc: Same. * config/loongarch/lasx.md: Same. * config/loongarch/lsx.md: Same. * config/loongarch/sync.md: Same. --- gcc/config/loongarch/genopts/genstr.sh | 2 +- gcc/config/loongarch/genopts/loongarch.opt.in | 6 ++--- gcc/config/loongarch/lasx.md | 4 ++-- gcc/config/loongarch/loongarch-builtins.cc | 6 ++--- gcc/config/loongarch/loongarch-c.cc | 2 +- gcc/config/loongarch/loongarch-def.h | 5 +++- gcc/config/loongarch/loongarch-driver.cc | 5 ++-- gcc/config/loongarch/loongarch-opts.cc | 17 ++++++++++++- gcc/config/loongarch/loongarch-opts.h | 24 +++++++++++++++---- gcc/config/loongarch/loongarch.cc | 24 ++++++++----------- gcc/config/loongarch/loongarch.md | 12 +++++----- gcc/config/loongarch/loongarch.opt | 16 ++++++------- gcc/config/loongarch/lsx.md | 4 ++-- gcc/config/loongarch/sync.md | 22 ++++++++--------- 14 files changed, 90 insertions(+), 59 deletions(-) diff --git a/gcc/config/loongarch/genopts/genstr.sh b/gcc/config/loongarch/genopts/genstr.sh index 5865b87d516..724c9aaedac 100755 --- a/gcc/config/loongarch/genopts/genstr.sh +++ b/gcc/config/loongarch/genopts/genstr.sh @@ -107,7 +107,7 @@ EOF print("") print("m"$3) gsub(/-/, "_", $3) - print("Target Mask(ISA_"toupper($3)") Var(isa_evolution)") + print("Target Mask(ISA_"toupper($3)") Var(la_isa_evolution)") $1=""; $2=""; $3="" sub(/^ */, "", $0) print($0) diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index f2e7ea2ef2f..e643deacd21 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -259,6 +259,6 @@ default value is 4. ; Features added during ISA evolution. This concept is different from ISA ; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the ; explanation. These features may be implemented and enumerated with -; CPUCFG independantly, so we use bit flags to specify them. -Variable -HOST_WIDE_INT isa_evolution = 0 +; CPUCFG independently, so we use bit flags to specify them. +TargetVariable +HOST_WIDE_INT la_isa_evolution = 0 diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 027021b45d5..429c59504b9 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -1539,7 +1539,7 @@ (define_insn "lasx_xvfrecipe_" [(set (match_operand:FLASX 0 "register_operand" "=f") (unspec:FLASX [(match_operand:FLASX 1 "register_operand" "f")] UNSPEC_LASX_XVFRECIPE))] - "ISA_HAS_LASX && TARGET_FRECIPE" + "ISA_HAS_LASX && ISA_HAS_FRECIPE" "xvfrecipe.\t%u0,%u1" [(set_attr "type" "simd_fdiv") (set_attr "mode" "")]) @@ -1572,7 +1572,7 @@ (define_insn "lasx_xvfrsqrte_" [(set (match_operand:FLASX 0 "register_operand" "=f") (unspec:FLASX [(match_operand:FLASX 1 "register_operand" "f")] UNSPEC_LASX_XVFRSQRTE))] - "ISA_HAS_LASX && TARGET_FRECIPE" + "ISA_HAS_LASX && ISA_HAS_FRECIPE" "xvfrsqrte.\t%u0,%u1" [(set_attr "type" "simd_fdiv") (set_attr "mode" "")]) diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc index 45ec6aca030..efe7e5e5ebc 100644 --- a/gcc/config/loongarch/loongarch-builtins.cc +++ b/gcc/config/loongarch/loongarch-builtins.cc @@ -120,9 +120,9 @@ struct loongarch_builtin_description AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI) AVAIL_ALL (lsx, ISA_HAS_LSX) AVAIL_ALL (lasx, ISA_HAS_LASX) -AVAIL_ALL (frecipe, TARGET_FRECIPE && TARGET_HARD_FLOAT_ABI) -AVAIL_ALL (lsx_frecipe, ISA_HAS_LSX && TARGET_FRECIPE) -AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && TARGET_FRECIPE) +AVAIL_ALL (frecipe, ISA_HAS_FRECIPE && TARGET_HARD_FLOAT_ABI) +AVAIL_ALL (lsx_frecipe, ISA_HAS_LSX && ISA_HAS_FRECIPE) +AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE) /* Construct a loongarch_builtin_description from the given arguments. diff --git a/gcc/config/loongarch/loongarch-c.cc b/gcc/config/loongarch/loongarch-c.cc index 118b1512e1e..4d88c1729ff 100644 --- a/gcc/config/loongarch/loongarch-c.cc +++ b/gcc/config/loongarch/loongarch-c.cc @@ -102,7 +102,7 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile) else builtin_define ("__loongarch_frlen=0"); - if (TARGET_HARD_FLOAT && TARGET_FRECIPE) + if (TARGET_HARD_FLOAT && ISA_HAS_FRECIPE) builtin_define ("__loongarch_frecipe"); if (ISA_HAS_LSX) diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index 403b024812d..1fab4f4d315 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -132,8 +132,11 @@ struct loongarch_isa Using int64_t instead of HOST_WIDE_INT for C compatibility. */ int64_t evolution; + int64_t evolution_set; - loongarch_isa () : base (0), fpu (0), simd (0), evolution (0) {} + loongarch_isa () : + base (0), fpu (0), simd (0), evolution (0), evolution_set (0) + {} loongarch_isa base_ (int _base) { base = _base; return *this; } loongarch_isa fpu_ (int _fpu) { fpu = _fpu; return *this; } loongarch_isa simd_ (int _simd) { simd = _simd; return *this; } diff --git a/gcc/config/loongarch/loongarch-driver.cc b/gcc/config/loongarch/loongarch-driver.cc index ef1db3104e7..62658f531ad 100644 --- a/gcc/config/loongarch/loongarch-driver.cc +++ b/gcc/config/loongarch/loongarch-driver.cc @@ -42,9 +42,10 @@ extern struct obstack opts_obstack; const char* la_driver_init (int argc ATTRIBUTE_UNUSED, const char **argv ATTRIBUTE_UNUSED) { - /* Initialize all fields of la_target to -1 */ + /* Initialize all fields of la_target. */ loongarch_init_target (&la_target, M_OPT_UNSET, M_OPT_UNSET, M_OPT_UNSET, - M_OPT_UNSET, M_OPT_UNSET, M_OPT_UNSET, M_OPT_UNSET); + M_OPT_UNSET, M_OPT_UNSET, M_OPT_UNSET, M_OPT_UNSET, + 0, 0); return ""; } diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc index d28b4363c7b..9483060ab62 100644 --- a/gcc/config/loongarch/loongarch-opts.cc +++ b/gcc/config/loongarch/loongarch-opts.cc @@ -140,7 +140,9 @@ static int with_default_simd = 0; void loongarch_init_target (struct loongarch_target *target, int cpu_arch, int cpu_tune, int fpu, int simd, - int abi_base, int abi_ext, int cmodel) + int abi_base, int abi_ext, int cmodel, + HOST_WIDE_INT isa_evolution, + HOST_WIDE_INT isa_evolution_set) { if (!target) return; @@ -148,6 +150,8 @@ loongarch_init_target (struct loongarch_target *target, target->cpu_tune = cpu_tune; target->isa.fpu = fpu; target->isa.simd = simd; + target->isa.evolution = isa_evolution; + target->isa.evolution_set = isa_evolution_set; target->abi.base = abi_base; target->abi.ext = abi_ext; target->cmodel = cmodel; @@ -184,6 +188,9 @@ loongarch_config_target (struct loongarch_target *target, M_OPT_ABSENT (target->abi.base) ? 0 : 1, }; + int64_t isa_evolution = target->isa.evolution; + int64_t isa_evolution_set = target->isa.evolution_set; + /* 1. Target ABI */ if (constrained.abi_base) t.abi.base = target->abi.base; @@ -394,6 +401,13 @@ config_target_isa: } } + /* Apply the ISA evolution feature switches from the user. */ + HOST_WIDE_INT isa_evolution_orig = t.isa.evolution; + t.isa.evolution &= ~(~isa_evolution & isa_evolution_set); + t.isa.evolution |= isa_evolution & isa_evolution_set; + + /* evolution_set means "what's different from the -march default". */ + t.isa.evolution_set = isa_evolution_orig ^ t.isa.evolution; /* 4. ABI-ISA compatibility */ /* Note: @@ -774,4 +788,5 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target, /* status of -mfpu */ opts->x_la_opt_fpu = target->isa.fpu; opts->x_la_opt_simd = target->isa.simd; + opts->x_la_isa_evolution = target->isa.evolution; } diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h index b28dcbfb791..aa0dd32f411 100644 --- a/gcc/config/loongarch/loongarch-opts.h +++ b/gcc/config/loongarch/loongarch-opts.h @@ -34,7 +34,9 @@ extern struct loongarch_target la_target; void loongarch_init_target (struct loongarch_target *target, int cpu_arch, int cpu_tune, int fpu, int simd, - int abi_base, int abi_ext, int cmodel); + int abi_base, int abi_ext, int cmodel, + HOST_WIDE_INT isa_evolutions, + HOST_WIDE_INT isa_evolutions_set); /* Handler for "-m" option combinations, @@ -82,9 +84,23 @@ struct loongarch_flags { || la_target.abi.base == ABI_BASE_LP64F \ || la_target.abi.base == ABI_BASE_LP64S) -#define ISA_HAS_LSX (la_target.isa.simd == ISA_EXT_SIMD_LSX \ - || la_target.isa.simd == ISA_EXT_SIMD_LASX) -#define ISA_HAS_LASX (la_target.isa.simd == ISA_EXT_SIMD_LASX) +#define ISA_HAS_LSX \ + (la_target.isa.simd == ISA_EXT_SIMD_LSX \ + || la_target.isa.simd == ISA_EXT_SIMD_LASX) + +#define ISA_HAS_LASX \ + (la_target.isa.simd == ISA_EXT_SIMD_LASX) + +#define ISA_HAS_FRECIPE \ + (la_target.isa.evolution & OPTION_MASK_ISA_FRECIPE) +#define ISA_HAS_DIV32 \ + (la_target.isa.evolution & OPTION_MASK_ISA_DIV32) +#define ISA_HAS_LAM_BH \ + (la_target.isa.evolution & OPTION_MASK_ISA_LAM_BH) +#define ISA_HAS_LAMCAS \ + (la_target.isa.evolution & OPTION_MASK_ISA_LAMCAS) +#define ISA_HAS_LD_SEQ_SA \ + (la_target.isa.evolution & OPTION_MASK_ISA_LD_SEQ_SA) /* TARGET_ macros for use in *.md template conditionals */ #define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 91e6bb3e95a..95517ec61da 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -3874,7 +3874,7 @@ loongarch_rtx_costs (rtx x, machine_mode mode, int outer_code, else { *total = loongarch_cost->int_div_si; - if (TARGET_64BIT && !TARGET_DIV32) + if (TARGET_64BIT && !ISA_HAS_DIV32) *total += COSTS_N_INSNS (2); } @@ -6122,7 +6122,7 @@ loongarch_print_operand (FILE *file, rtx op, int letter) if (loongarch_cas_failure_memorder_needs_acquire ( memmodel_from_int (INTVAL (op)))) fputs ("dbar\t0b10100", file); - else if (!TARGET_LD_SEQ_SA) + else if (!ISA_HAS_LD_SEQ_SA) fputs ("dbar\t0x700", file); break; @@ -7524,7 +7524,8 @@ loongarch_option_override_internal (struct gcc_options *opts, loongarch_init_target (&la_target, la_opt_cpu_arch, la_opt_cpu_tune, la_opt_fpu, la_opt_simd, la_opt_abi_base, la_opt_abi_ext, - la_opt_cmodel); + la_opt_cmodel, opts->x_la_isa_evolution, + opts_set->x_la_isa_evolution); /* Handle target-specific options: compute defaults/conflicts etc. */ loongarch_config_target (&la_target, NULL, 0); @@ -7565,11 +7566,6 @@ loongarch_option_override_internal (struct gcc_options *opts, if (loongarch_branch_cost == 0) loongarch_branch_cost = loongarch_cost->branch_cost; - /* If the user hasn't disabled a feature added during ISA evolution, - use the processor's default. */ - isa_evolution |= (la_target.isa.evolution & - ~global_options_set.x_isa_evolution); - /* Enable sw prefetching at -O3 and higher. */ if (opts->x_flag_prefetch_loop_arrays < 0 && (opts->x_optimize >= 3 || opts->x_flag_profile_use) @@ -7700,7 +7696,7 @@ loongarch_option_override_internal (struct gcc_options *opts, } if (loongarch_recip) recip_mask |= RECIP_MASK_ALL; - if (!TARGET_FRECIPE) + if (!ISA_HAS_FRECIPE) recip_mask = RECIP_MASK_NONE; } @@ -11743,11 +11739,11 @@ loongarch_asm_code_end (void) loongarch_cpu_strings [la_target.cpu_tune]); fprintf (asm_out_file, "%s Base ISA: %s\n", ASM_COMMENT_START, loongarch_isa_base_strings [la_target.isa.base]); - DUMP_FEATURE (TARGET_FRECIPE); - DUMP_FEATURE (TARGET_DIV32); - DUMP_FEATURE (TARGET_LAM_BH); - DUMP_FEATURE (TARGET_LAMCAS); - DUMP_FEATURE (TARGET_LD_SEQ_SA); + DUMP_FEATURE (ISA_HAS_FRECIPE); + DUMP_FEATURE (ISA_HAS_DIV32); + DUMP_FEATURE (ISA_HAS_LAM_BH); + DUMP_FEATURE (ISA_HAS_LAMCAS); + DUMP_FEATURE (ISA_HAS_LD_SEQ_SA); } fputs ("\n\n", asm_out_file); diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index d1f5b94f5d6..8510f24835b 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -425,7 +425,7 @@ (define_mode_iterator ST_ANY [QHWD ANYF]) ;; A mode for anything legal as a input of a div or mod instruction. (define_mode_iterator DIV [(DI "TARGET_64BIT") - (SI "!TARGET_64BIT || TARGET_DIV32")]) + (SI "!TARGET_64BIT || ISA_HAS_DIV32")]) ;; In GPR templates, a string like "mul." will expand to "mul.w" in the ;; 32-bit version and "mul.d" in the 64-bit version. @@ -941,7 +941,7 @@ (define_insn "loongarch_frecipe_" [(set (match_operand:ANYF 0 "register_operand" "=f") (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] UNSPEC_RECIPE))] - "TARGET_FRECIPE" + "ISA_HAS_FRECIPE" "frecipe.\t%0,%1" [(set_attr "type" "frecipe") (set_attr "mode" "") @@ -954,7 +954,7 @@ (define_expand "3" (match_operand:GPR 2 "register_operand")))] "" { - if (GET_MODE (operands[0]) == SImode && TARGET_64BIT && !TARGET_DIV32) + if (GET_MODE (operands[0]) == SImode && TARGET_64BIT && !ISA_HAS_DIV32) { rtx reg1 = gen_reg_rtx (DImode); rtx reg2 = gen_reg_rtx (DImode); @@ -994,7 +994,7 @@ (define_insn "si3_extended" (sign_extend (any_div:SI (match_operand:SI 1 "register_operand" "r,r,0") (match_operand:SI 2 "register_operand" "r,r,r"))))] - "TARGET_64BIT && TARGET_DIV32" + "TARGET_64BIT && ISA_HAS_DIV32" { return loongarch_output_division (".w\t%0,%1,%2", operands); } @@ -1014,7 +1014,7 @@ (define_insn "di3_fake" (any_div:DI (match_operand:DI 1 "register_operand" "r,r,0") (match_operand:DI 2 "register_operand" "r,r,r")) 0)] UNSPEC_FAKE_ANY_DIV)))] - "TARGET_64BIT && !TARGET_DIV32" + "TARGET_64BIT && !ISA_HAS_DIV32" { return loongarch_output_division (".w\t%0,%1,%2", operands); } @@ -1197,7 +1197,7 @@ (define_insn "loongarch_frsqrte_" [(set (match_operand:ANYF 0 "register_operand" "=f") (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] UNSPEC_RSQRTE))] - "TARGET_FRECIPE" + "ISA_HAS_FRECIPE" "frsqrte.\t%0,%1" [(set_attr "type" "frsqrte") (set_attr "mode" "")]) diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index b285a74acea..8b36f1a1495 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -267,26 +267,26 @@ default value is 4. ; Features added during ISA evolution. This concept is different from ISA ; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the ; explanation. These features may be implemented and enumerated with -; CPUCFG independantly, so we use bit flags to specify them. -Variable -HOST_WIDE_INT isa_evolution = 0 +; CPUCFG independently, so we use bit flags to specify them. +TargetVariable +HOST_WIDE_INT la_isa_evolution = 0 mfrecipe -Target Mask(ISA_FRECIPE) Var(isa_evolution) +Target Mask(ISA_FRECIPE) Var(la_isa_evolution) Support frecipe.{s/d} and frsqrte.{s/d} instructions. mdiv32 -Target Mask(ISA_DIV32) Var(isa_evolution) +Target Mask(ISA_DIV32) Var(la_isa_evolution) Support div.w[u] and mod.w[u] instructions with inputs not sign-extended. mlam-bh -Target Mask(ISA_LAM_BH) Var(isa_evolution) +Target Mask(ISA_LAM_BH) Var(la_isa_evolution) Support am{swap/add}[_db].{b/h} instructions. mlamcas -Target Mask(ISA_LAMCAS) Var(isa_evolution) +Target Mask(ISA_LAMCAS) Var(la_isa_evolution) Support amcas[_db].{b/h/w/d} instructions. mld-seq-sa -Target Mask(ISA_LD_SEQ_SA) Var(isa_evolution) +Target Mask(ISA_LD_SEQ_SA) Var(la_isa_evolution) Do not need load-load barriers (dbar 0x700). diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index 76d33a3b88a..a1632accdd9 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -1505,7 +1505,7 @@ (define_insn "lsx_vfrecipe_" [(set (match_operand:FLSX 0 "register_operand" "=f") (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")] UNSPEC_LSX_VFRECIPE))] - "ISA_HAS_LSX && TARGET_FRECIPE" + "ISA_HAS_LSX && ISA_HAS_FRECIPE" "vfrecipe.\t%w0,%w1" [(set_attr "type" "simd_fdiv") (set_attr "mode" "")]) @@ -1538,7 +1538,7 @@ (define_insn "lsx_vfrsqrte_" [(set (match_operand:FLSX 0 "register_operand" "=f") (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")] UNSPEC_LSX_VFRSQRTE))] - "ISA_HAS_LSX && TARGET_FRECIPE" + "ISA_HAS_LSX && ISA_HAS_FRECIPE" "vfrsqrte.\t%w0,%w1" [(set_attr "type" "simd_fdiv") (set_attr "mode" "")]) diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md index 71954f95f59..8f35a5b48d2 100644 --- a/gcc/config/loongarch/sync.md +++ b/gcc/config/loongarch/sync.md @@ -124,9 +124,9 @@ (define_insn "atomic_load" return "ld.\t%0,%1\\n\\t" "dbar\t0x14"; case MEMMODEL_RELAXED: - return TARGET_LD_SEQ_SA ? "ld.\t%0,%1" - : "ld.\t%0,%1\\n\\t" - "dbar\t0x700"; + return ISA_HAS_LD_SEQ_SA ? "ld.\t%0,%1" + : "ld.\t%0,%1\\n\\t" + "dbar\t0x700"; default: /* The valid memory order variants are __ATOMIC_RELAXED, __ATOMIC_SEQ_CST, @@ -193,7 +193,7 @@ (define_insn "atomic_add" (match_operand:SHORT 1 "reg_or_0_operand" "rJ")) (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] - "TARGET_LAM_BH" + "ISA_HAS_LAM_BH" "amadd%A2.\t$zero,%z1,%0" [(set (attr "length") (const_int 4))]) @@ -230,7 +230,7 @@ (define_insn "atomic_exchange_short" UNSPEC_SYNC_EXCHANGE)) (set (match_dup 1) (match_operand:SHORT 2 "register_operand" "r"))] - "TARGET_LAM_BH" + "ISA_HAS_LAM_BH" "amswap%A3.\t%0,%z2,%1" [(set (attr "length") (const_int 4))]) @@ -266,7 +266,7 @@ (define_insn "atomic_cas_value_strong_amcas" (match_operand:QHWD 3 "reg_or_0_operand" "rJ") (match_operand:SI 4 "const_int_operand")] ;; mod_s UNSPEC_COMPARE_AND_SWAP))] - "TARGET_LAMCAS" + "ISA_HAS_LAMCAS" "ori\t%0,%z2,0\n\tamcas%A4.\t%0,%z3,%1" [(set (attr "length") (const_int 8))]) @@ -296,7 +296,7 @@ (define_expand "atomic_compare_and_swap" operands[6] = mod_s; - if (TARGET_LAMCAS) + if (ISA_HAS_LAMCAS) emit_insn (gen_atomic_cas_value_strong_amcas (operands[1], operands[2], operands[3], operands[4], operands[6])); @@ -422,7 +422,7 @@ (define_expand "atomic_compare_and_swap" operands[6] = mod_s; - if (TARGET_LAMCAS) + if (ISA_HAS_LAMCAS) emit_insn (gen_atomic_cas_value_strong_amcas (operands[1], operands[2], operands[3], operands[4], operands[6])); @@ -642,7 +642,7 @@ (define_expand "atomic_exchange" (match_operand:SHORT 2 "register_operand"))] "" { - if (TARGET_LAM_BH) + if (ISA_HAS_LAM_BH) emit_insn (gen_atomic_exchange_short (operands[0], operands[1], operands[2], operands[3])); else { @@ -663,7 +663,7 @@ (define_insn "atomic_fetch_add_short" (match_operand:SHORT 2 "reg_or_0_operand" "rJ")) (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] - "TARGET_LAM_BH" + "ISA_HAS_LAM_BH" "amadd%A3.\t%0,%z2,%1" [(set (attr "length") (const_int 4))]) @@ -678,7 +678,7 @@ (define_expand "atomic_fetch_add" UNSPEC_SYNC_OLD_OP))] "" { - if (TARGET_LAM_BH) + if (ISA_HAS_LAM_BH) emit_insn (gen_atomic_fetch_add_short (operands[0], operands[1], operands[2], operands[3])); else