diff mbox series

[v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

Message ID 20231229041943.1366-1-cooper.joshua@linux.alibaba.com
State New
Headers show
Series [v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector. | expand

Commit Message

joshua Dec. 29, 2023, 4:19 a.m. UTC 
This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions. We only check the
prefix is 'v', so that no extra attribute is needed.

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (riscv_asm_output_opcode): 
	New function to add assembler insn code prefix/suffix.
	* config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
	* config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.

Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/riscv-protos.h                    |  1 +
 gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
 gcc/config/riscv/riscv.h                           |  4 ++++
 .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
 4 files changed, 31 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c

Comments

Jeff Law Dec. 31, 2023, 5:43 p.m. UTC | #1 
On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> This patch adds th. prefix to all XTheadVector instructions by
> implementing new assembly output functions. We only check the
> prefix is 'v', so that no extra attribute is needed.
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> 	New function to add assembler insn code prefix/suffix.
> 	* config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> 	* config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> 
> Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>   gcc/config/riscv/riscv-protos.h                    |  1 +
>   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
>   gcc/config/riscv/riscv.h                           |  4 ++++
>   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
>   4 files changed, 31 insertions(+)
>   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> 
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 31049ef7523..5ea54b45703 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -102,6 +102,7 @@ struct riscv_address_info {
>   };
>   
>   /* Routines implemented in riscv.cc.  */
> +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
>   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
>   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
>   extern int riscv_float_const_rtx_index_for_fli (rtx);
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 0d1cbc5cb5f..ea1d59d9cf2 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
>     return lmul;
>   }
>   
> +/* Define ASM_OUTPUT_OPCODE to do anything special before
> +   emitting an opcode.  */
> +const char *
> +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> +{
> +  /* We need to add th. prefix to all the xtheadvector
> +     insturctions here.*/
> +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> +      p[0] == 'v')
> +    fputs ("th.", asm_out_file);
> +
> +  return p;
Just a formatting nit. The GNU standards break lines before the 
operator, not after.  So
   if (TARGET_XTHEADVECTOR
       && current_output_insn != NULL
       && p[0] == 'v')

Note that current_output_insn is "extern rtx_insn *", so use NULL, not 
NULL_RTX.

Neither of these nits require a new version for review.  Just fix them.

If Juzhe is fine with this, so am I.  We can refine it if necessary later.

jeff
juzhe.zhong@rivai.ai Jan. 1, 2024, 10:57 p.m. UTC | #2 
This is Ok from my side.
But before commit this patch, I think we need this patch first:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html 

I will be back to work so I will take a look at other patches today.


juzhe.zhong@rivai.ai
 
From: Jeff Law
Date: 2024-01-01 01:43
To: Jun Sha (Joshua); gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
 
 
On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> This patch adds th. prefix to all XTheadVector instructions by
> implementing new assembly output functions. We only check the
> prefix is 'v', so that no extra attribute is needed.
> 
> gcc/ChangeLog:
> 
> * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> New function to add assembler insn code prefix/suffix.
> * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> 
> Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>   gcc/config/riscv/riscv-protos.h                    |  1 +
>   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
>   gcc/config/riscv/riscv.h                           |  4 ++++
>   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
>   4 files changed, 31 insertions(+)
>   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> 
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 31049ef7523..5ea54b45703 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -102,6 +102,7 @@ struct riscv_address_info {
>   };
>   
>   /* Routines implemented in riscv.cc.  */
> +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
>   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
>   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
>   extern int riscv_float_const_rtx_index_for_fli (rtx);
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 0d1cbc5cb5f..ea1d59d9cf2 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
>     return lmul;
>   }
>   
> +/* Define ASM_OUTPUT_OPCODE to do anything special before
> +   emitting an opcode.  */
> +const char *
> +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> +{
> +  /* We need to add th. prefix to all the xtheadvector
> +     insturctions here.*/
> +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> +      p[0] == 'v')
> +    fputs ("th.", asm_out_file);
> +
> +  return p;
Just a formatting nit. The GNU standards break lines before the 
operator, not after.  So
   if (TARGET_XTHEADVECTOR
       && current_output_insn != NULL
       && p[0] == 'v')
 
Note that current_output_insn is "extern rtx_insn *", so use NULL, not 
NULL_RTX.
 
Neither of these nits require a new version for review.  Just fix them.
 
If Juzhe is fine with this, so am I.  We can refine it if necessary later.
 
jeff
Andrew Pinski Jan. 3, 2024, 2:54 a.m. UTC | #3 
On Mon, Jan 1, 2024 at 2:59 PM 钟居哲 <juzhe.zhong@rivai.ai> wrote:
>
> This is Ok from my side.
> But before commit this patch, I think we need this patch first:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
>
> I will be back to work so I will take a look at other patches today.


Note I hate it. It would be better if you use something like `%^' (see
`~` for an example of how that works) instead of hacking
riscv_asm_output_opcode really. In fact that is how other targets
implement this kind of things.

Thanks,
Andrew PInski

> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: Jeff Law
> Date: 2024-01-01 01:43
> To: Jun Sha (Joshua); gcc-patches
> CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
> Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
>
>
> On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> > This patch adds th. prefix to all XTheadVector instructions by
> > implementing new assembly output functions. We only check the
> > prefix is 'v', so that no extra attribute is needed.
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> > New function to add assembler insn code prefix/suffix.
> > * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> > * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> >
> > Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> > Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> > Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> >   gcc/config/riscv/riscv-protos.h                    |  1 +
> >   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
> >   gcc/config/riscv/riscv.h                           |  4 ++++
> >   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
> >   4 files changed, 31 insertions(+)
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> >
> > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> > index 31049ef7523..5ea54b45703 100644
> > --- a/gcc/config/riscv/riscv-protos.h
> > +++ b/gcc/config/riscv/riscv-protos.h
> > @@ -102,6 +102,7 @@ struct riscv_address_info {
> >   };
> >
> >   /* Routines implemented in riscv.cc.  */
> > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
> >   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
> >   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
> >   extern int riscv_float_const_rtx_index_for_fli (rtx);
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 0d1cbc5cb5f..ea1d59d9cf2 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
> >     return lmul;
> >   }
> >
> > +/* Define ASM_OUTPUT_OPCODE to do anything special before
> > +   emitting an opcode.  */
> > +const char *
> > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> > +{
> > +  /* We need to add th. prefix to all the xtheadvector
> > +     insturctions here.*/
> > +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> > +      p[0] == 'v')
> > +    fputs ("th.", asm_out_file);
> > +
> > +  return p;
> Just a formatting nit. The GNU standards break lines before the
> operator, not after.  So
>    if (TARGET_XTHEADVECTOR
>        && current_output_insn != NULL
>        && p[0] == 'v')
>
> Note that current_output_insn is "extern rtx_insn *", so use NULL, not
> NULL_RTX.
>
> Neither of these nits require a new version for review.  Just fix them.
>
> If Juzhe is fine with this, so am I.  We can refine it if necessary later.
>
> jeff
>
juzhe.zhong@rivai.ai Jan. 3, 2024, 3:06 a.m. UTC | #4 
We have no choice. You should know theadvector is totally unrelated with RVV1.0 standard ISA.

Adding `%^' which missing totally unrelated ISA makes no sens to me.



juzhe.zhong@rivai.ai
 
From: Andrew Pinski
Date: 2024-01-03 10:54
To: 钟居哲
CC: Jeff Law; cooper.joshua; gcc-patches; jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; Cooper Qu
Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
On Mon, Jan 1, 2024 at 2:59 PM 钟居哲 <juzhe.zhong@rivai.ai> wrote:
>
> This is Ok from my side.
> But before commit this patch, I think we need this patch first:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
>
> I will be back to work so I will take a look at other patches today.
 
 
Note I hate it. It would be better if you use something like `%^' (see
`~` for an example of how that works) instead of hacking
riscv_asm_output_opcode really. In fact that is how other targets
implement this kind of things.
 
Thanks,
Andrew PInski
 
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: Jeff Law
> Date: 2024-01-01 01:43
> To: Jun Sha (Joshua); gcc-patches
> CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
> Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
>
>
> On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> > This patch adds th. prefix to all XTheadVector instructions by
> > implementing new assembly output functions. We only check the
> > prefix is 'v', so that no extra attribute is needed.
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> > New function to add assembler insn code prefix/suffix.
> > * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> > * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> >
> > Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> > Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> > Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> >   gcc/config/riscv/riscv-protos.h                    |  1 +
> >   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
> >   gcc/config/riscv/riscv.h                           |  4 ++++
> >   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
> >   4 files changed, 31 insertions(+)
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> >
> > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> > index 31049ef7523..5ea54b45703 100644
> > --- a/gcc/config/riscv/riscv-protos.h
> > +++ b/gcc/config/riscv/riscv-protos.h
> > @@ -102,6 +102,7 @@ struct riscv_address_info {
> >   };
> >
> >   /* Routines implemented in riscv.cc.  */
> > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
> >   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
> >   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
> >   extern int riscv_float_const_rtx_index_for_fli (rtx);
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 0d1cbc5cb5f..ea1d59d9cf2 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
> >     return lmul;
> >   }
> >
> > +/* Define ASM_OUTPUT_OPCODE to do anything special before
> > +   emitting an opcode.  */
> > +const char *
> > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> > +{
> > +  /* We need to add th. prefix to all the xtheadvector
> > +     insturctions here.*/
> > +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> > +      p[0] == 'v')
> > +    fputs ("th.", asm_out_file);
> > +
> > +  return p;
> Just a formatting nit. The GNU standards break lines before the
> operator, not after.  So
>    if (TARGET_XTHEADVECTOR
>        && current_output_insn != NULL
>        && p[0] == 'v')
>
> Note that current_output_insn is "extern rtx_insn *", so use NULL, not
> NULL_RTX.
>
> Neither of these nits require a new version for review.  Just fix them.
>
> If Juzhe is fine with this, so am I.  We can refine it if necessary later.
>
> jeff
>
Andrew Pinski Jan. 3, 2024, 3:19 a.m. UTC | #5 
On Tue, Jan 2, 2024 at 7:07 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> We have no choice. You should know theadvector is totally unrelated with RVV1.0 standard ISA.
>
> Adding `%^' which missing totally unrelated ISA makes no sens to me.

No, it implements it in a different way.
Basically all of the patterns which are supported get changed to be
instead of "v*" becomes instead "%^v" and then you change
riscv_print_operand_punct_valid_p to allow '^' and then you add '^'
support to riscv_print_operand (like '~' is handled there).

And the next patch adds a few more '%' to support printing different
different strings based on XTheadVector or not.

This is how almost all other targets handle this kind of things
instead of hacking ASM_OUTPUT_OPCODE .

Thanks,
Andrew Pinski


>
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: Andrew Pinski
> Date: 2024-01-03 10:54
> To: 钟居哲
> CC: Jeff Law; cooper.joshua; gcc-patches; jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; Cooper Qu
> Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> On Mon, Jan 1, 2024 at 2:59 PM 钟居哲 <juzhe.zhong@rivai.ai> wrote:
> >
> > This is Ok from my side.
> > But before commit this patch, I think we need this patch first:
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
> >
> > I will be back to work so I will take a look at other patches today.
>
>
> Note I hate it. It would be better if you use something like `%^' (see
> `~` for an example of how that works) instead of hacking
> riscv_asm_output_opcode really. In fact that is how other targets
> implement this kind of things.
>
> Thanks,
> Andrew PInski
>
> > ________________________________
> > juzhe.zhong@rivai.ai
> >
> >
> > From: Jeff Law
> > Date: 2024-01-01 01:43
> > To: Jun Sha (Joshua); gcc-patches
> > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
> > Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> >
> >
> > On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> > > This patch adds th. prefix to all XTheadVector instructions by
> > > implementing new assembly output functions. We only check the
> > > prefix is 'v', so that no extra attribute is needed.
> > >
> > > gcc/ChangeLog:
> > >
> > > * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> > > New function to add assembler insn code prefix/suffix.
> > > * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> > > * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> > >
> > > Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> > > Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> > > Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > > ---
> > >   gcc/config/riscv/riscv-protos.h                    |  1 +
> > >   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
> > >   gcc/config/riscv/riscv.h                           |  4 ++++
> > >   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
> > >   4 files changed, 31 insertions(+)
> > >   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> > >
> > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> > > index 31049ef7523..5ea54b45703 100644
> > > --- a/gcc/config/riscv/riscv-protos.h
> > > +++ b/gcc/config/riscv/riscv-protos.h
> > > @@ -102,6 +102,7 @@ struct riscv_address_info {
> > >   };
> > >
> > >   /* Routines implemented in riscv.cc.  */
> > > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
> > >   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
> > >   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
> > >   extern int riscv_float_const_rtx_index_for_fli (rtx);
> > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > > index 0d1cbc5cb5f..ea1d59d9cf2 100644
> > > --- a/gcc/config/riscv/riscv.cc
> > > +++ b/gcc/config/riscv/riscv.cc
> > > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
> > >     return lmul;
> > >   }
> > >
> > > +/* Define ASM_OUTPUT_OPCODE to do anything special before
> > > +   emitting an opcode.  */
> > > +const char *
> > > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> > > +{
> > > +  /* We need to add th. prefix to all the xtheadvector
> > > +     insturctions here.*/
> > > +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> > > +      p[0] == 'v')
> > > +    fputs ("th.", asm_out_file);
> > > +
> > > +  return p;
> > Just a formatting nit. The GNU standards break lines before the
> > operator, not after.  So
> >    if (TARGET_XTHEADVECTOR
> >        && current_output_insn != NULL
> >        && p[0] == 'v')
> >
> > Note that current_output_insn is "extern rtx_insn *", so use NULL, not
> > NULL_RTX.
> >
> > Neither of these nits require a new version for review.  Just fix them.
> >
> > If Juzhe is fine with this, so am I.  We can refine it if necessary later.
> >
> > jeff
> >
>
juzhe.zhong@rivai.ai Jan. 3, 2024, 3:25 a.m. UTC | #6 
No. It will need to change all patterns in vector.md.
It's a nightmare.

You should note I will refine vector.md in GCC-15, mixing theadvector things make me impossible to maintain
RVV1.0.



juzhe.zhong@rivai.ai
 
From: Andrew Pinski
Date: 2024-01-03 11:19
To: juzhe.zhong@rivai.ai
CC: jeffreyalaw; cooper.joshua; gcc-patches; Jim Wilson; palmer; andrew; philipp.tomsich; christoph.muellner; jinma; cooper.qu
Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
On Tue, Jan 2, 2024 at 7:07 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> We have no choice. You should know theadvector is totally unrelated with RVV1.0 standard ISA.
>
> Adding `%^' which missing totally unrelated ISA makes no sens to me.
 
No, it implements it in a different way.
Basically all of the patterns which are supported get changed to be
instead of "v*" becomes instead "%^v" and then you change
riscv_print_operand_punct_valid_p to allow '^' and then you add '^'
support to riscv_print_operand (like '~' is handled there).
 
And the next patch adds a few more '%' to support printing different
different strings based on XTheadVector or not.
 
This is how almost all other targets handle this kind of things
instead of hacking ASM_OUTPUT_OPCODE .
 
Thanks,
Andrew Pinski
 
 
>
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: Andrew Pinski
> Date: 2024-01-03 10:54
> To: 钟居哲
> CC: Jeff Law; cooper.joshua; gcc-patches; jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; Cooper Qu
> Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> On Mon, Jan 1, 2024 at 2:59 PM 钟居哲 <juzhe.zhong@rivai.ai> wrote:
> >
> > This is Ok from my side.
> > But before commit this patch, I think we need this patch first:
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
> >
> > I will be back to work so I will take a look at other patches today.
>
>
> Note I hate it. It would be better if you use something like `%^' (see
> `~` for an example of how that works) instead of hacking
> riscv_asm_output_opcode really. In fact that is how other targets
> implement this kind of things.
>
> Thanks,
> Andrew PInski
>
> > ________________________________
> > juzhe.zhong@rivai.ai
> >
> >
> > From: Jeff Law
> > Date: 2024-01-01 01:43
> > To: Jun Sha (Joshua); gcc-patches
> > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
> > Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> >
> >
> > On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> > > This patch adds th. prefix to all XTheadVector instructions by
> > > implementing new assembly output functions. We only check the
> > > prefix is 'v', so that no extra attribute is needed.
> > >
> > > gcc/ChangeLog:
> > >
> > > * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> > > New function to add assembler insn code prefix/suffix.
> > > * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> > > * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> > >
> > > Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> > > Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> > > Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > > ---
> > >   gcc/config/riscv/riscv-protos.h                    |  1 +
> > >   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
> > >   gcc/config/riscv/riscv.h                           |  4 ++++
> > >   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
> > >   4 files changed, 31 insertions(+)
> > >   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> > >
> > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> > > index 31049ef7523..5ea54b45703 100644
> > > --- a/gcc/config/riscv/riscv-protos.h
> > > +++ b/gcc/config/riscv/riscv-protos.h
> > > @@ -102,6 +102,7 @@ struct riscv_address_info {
> > >   };
> > >
> > >   /* Routines implemented in riscv.cc.  */
> > > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
> > >   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
> > >   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
> > >   extern int riscv_float_const_rtx_index_for_fli (rtx);
> > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > > index 0d1cbc5cb5f..ea1d59d9cf2 100644
> > > --- a/gcc/config/riscv/riscv.cc
> > > +++ b/gcc/config/riscv/riscv.cc
> > > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
> > >     return lmul;
> > >   }
> > >
> > > +/* Define ASM_OUTPUT_OPCODE to do anything special before
> > > +   emitting an opcode.  */
> > > +const char *
> > > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> > > +{
> > > +  /* We need to add th. prefix to all the xtheadvector
> > > +     insturctions here.*/
> > > +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> > > +      p[0] == 'v')
> > > +    fputs ("th.", asm_out_file);
> > > +
> > > +  return p;
> > Just a formatting nit. The GNU standards break lines before the
> > operator, not after.  So
> >    if (TARGET_XTHEADVECTOR
> >        && current_output_insn != NULL
> >        && p[0] == 'v')
> >
> > Note that current_output_insn is "extern rtx_insn *", so use NULL, not
> > NULL_RTX.
> >
> > Neither of these nits require a new version for review.  Just fix them.
> >
> > If Juzhe is fine with this, so am I.  We can refine it if necessary later.
> >
> > jeff
> >
>
Andrew Pinski Jan. 3, 2024, 3:32 a.m. UTC | #7 
On Tue, Jan 2, 2024 at 7:26 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> No. It will need to change all patterns in vector.md.
> It's a nightmare.
>
> You should note I will refine vector.md in GCC-15, mixing theadvector things make me impossible to maintain
> RVV1.0.

Then we should not support theadvector if things are getting this
messy. Both ways are hacks really.
Either way we need a better way of implementing this. Hacking
theadvector support using rewriting is wrong and not maintainable
either.
I suspect we should wait on supporting theadvector until GCC 15 anyways.

Thanks,
Andrew Pinski

>
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: Andrew Pinski
> Date: 2024-01-03 11:19
> To: juzhe.zhong@rivai.ai
> CC: jeffreyalaw; cooper.joshua; gcc-patches; Jim Wilson; palmer; andrew; philipp.tomsich; christoph.muellner; jinma; cooper.qu
> Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> On Tue, Jan 2, 2024 at 7:07 PM juzhe.zhong@rivai.ai
> <juzhe.zhong@rivai.ai> wrote:
> >
> > We have no choice. You should know theadvector is totally unrelated with RVV1.0 standard ISA.
> >
> > Adding `%^' which missing totally unrelated ISA makes no sens to me.
>
> No, it implements it in a different way.
> Basically all of the patterns which are supported get changed to be
> instead of "v*" becomes instead "%^v" and then you change
> riscv_print_operand_punct_valid_p to allow '^' and then you add '^'
> support to riscv_print_operand (like '~' is handled there).
>
> And the next patch adds a few more '%' to support printing different
> different strings based on XTheadVector or not.
>
> This is how almost all other targets handle this kind of things
> instead of hacking ASM_OUTPUT_OPCODE .
>
> Thanks,
> Andrew Pinski
>
>
> >
> > ________________________________
> > juzhe.zhong@rivai.ai
> >
> >
> > From: Andrew Pinski
> > Date: 2024-01-03 10:54
> > To: 钟居哲
> > CC: Jeff Law; cooper.joshua; gcc-patches; jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; Cooper Qu
> > Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> > On Mon, Jan 1, 2024 at 2:59 PM 钟居哲 <juzhe.zhong@rivai.ai> wrote:
> > >
> > > This is Ok from my side.
> > > But before commit this patch, I think we need this patch first:
> > > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
> > >
> > > I will be back to work so I will take a look at other patches today.
> >
> >
> > Note I hate it. It would be better if you use something like `%^' (see
> > `~` for an example of how that works) instead of hacking
> > riscv_asm_output_opcode really. In fact that is how other targets
> > implement this kind of things.
> >
> > Thanks,
> > Andrew PInski
> >
> > > ________________________________
> > > juzhe.zhong@rivai.ai
> > >
> > >
> > > From: Jeff Law
> > > Date: 2024-01-01 01:43
> > > To: Jun Sha (Joshua); gcc-patches
> > > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
> > > Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> > >
> > >
> > > On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> > > > This patch adds th. prefix to all XTheadVector instructions by
> > > > implementing new assembly output functions. We only check the
> > > > prefix is 'v', so that no extra attribute is needed.
> > > >
> > > > gcc/ChangeLog:
> > > >
> > > > * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> > > > New function to add assembler insn code prefix/suffix.
> > > > * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> > > > * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> > > >
> > > > Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> > > > Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> > > > Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > > > ---
> > > >   gcc/config/riscv/riscv-protos.h                    |  1 +
> > > >   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
> > > >   gcc/config/riscv/riscv.h                           |  4 ++++
> > > >   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
> > > >   4 files changed, 31 insertions(+)
> > > >   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> > > >
> > > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> > > > index 31049ef7523..5ea54b45703 100644
> > > > --- a/gcc/config/riscv/riscv-protos.h
> > > > +++ b/gcc/config/riscv/riscv-protos.h
> > > > @@ -102,6 +102,7 @@ struct riscv_address_info {
> > > >   };
> > > >
> > > >   /* Routines implemented in riscv.cc.  */
> > > > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
> > > >   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
> > > >   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
> > > >   extern int riscv_float_const_rtx_index_for_fli (rtx);
> > > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > > > index 0d1cbc5cb5f..ea1d59d9cf2 100644
> > > > --- a/gcc/config/riscv/riscv.cc
> > > > +++ b/gcc/config/riscv/riscv.cc
> > > > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
> > > >     return lmul;
> > > >   }
> > > >
> > > > +/* Define ASM_OUTPUT_OPCODE to do anything special before
> > > > +   emitting an opcode.  */
> > > > +const char *
> > > > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> > > > +{
> > > > +  /* We need to add th. prefix to all the xtheadvector
> > > > +     insturctions here.*/
> > > > +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> > > > +      p[0] == 'v')
> > > > +    fputs ("th.", asm_out_file);
> > > > +
> > > > +  return p;
> > > Just a formatting nit. The GNU standards break lines before the
> > > operator, not after.  So
> > >    if (TARGET_XTHEADVECTOR
> > >        && current_output_insn != NULL
> > >        && p[0] == 'v')
> > >
> > > Note that current_output_insn is "extern rtx_insn *", so use NULL, not
> > > NULL_RTX.
> > >
> > > Neither of these nits require a new version for review.  Just fix them.
> > >
> > > If Juzhe is fine with this, so am I.  We can refine it if necessary later.
> > >
> > > jeff
> > >
> >
>
Kito Cheng Jan. 3, 2024, 3:32 a.m. UTC | #8 
Hi Andrew:

That's kinda compromise and trade off on the t-head vector stuffs, we
would like to accept that, but without disturbing the vector 1.0
implementation too much, t-head vector is transitional product and it
will freeze/stop there forever without extending new stuffs like
vector bfloat and vector crypto stuffs.

So we think using ASM_OUTPUT_OPCODE is better in this case rather than
adding %^ to every vector pattern for the t-head vector.

On Wed, Jan 3, 2024 at 11:26 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> No. It will need to change all patterns in vector.md.
> It's a nightmare.
>
> You should note I will refine vector.md in GCC-15, mixing theadvector things make me impossible to maintain
> RVV1.0.
>
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: Andrew Pinski
> Date: 2024-01-03 11:19
> To: juzhe.zhong@rivai.ai
> CC: jeffreyalaw; cooper.joshua; gcc-patches; Jim Wilson; palmer; andrew; philipp.tomsich; christoph.muellner; jinma; cooper.qu
> Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> On Tue, Jan 2, 2024 at 7:07 PM juzhe.zhong@rivai.ai
> <juzhe.zhong@rivai.ai> wrote:
> >
> > We have no choice. You should know theadvector is totally unrelated with RVV1.0 standard ISA.
> >
> > Adding `%^' which missing totally unrelated ISA makes no sens to me.
>
> No, it implements it in a different way.
> Basically all of the patterns which are supported get changed to be
> instead of "v*" becomes instead "%^v" and then you change
> riscv_print_operand_punct_valid_p to allow '^' and then you add '^'
> support to riscv_print_operand (like '~' is handled there).
>
> And the next patch adds a few more '%' to support printing different
> different strings based on XTheadVector or not.
>
> This is how almost all other targets handle this kind of things
> instead of hacking ASM_OUTPUT_OPCODE .
>
> Thanks,
> Andrew Pinski
>
>
> >
> > ________________________________
> > juzhe.zhong@rivai.ai
> >
> >
> > From: Andrew Pinski
> > Date: 2024-01-03 10:54
> > To: 钟居哲
> > CC: Jeff Law; cooper.joshua; gcc-patches; jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; Cooper Qu
> > Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> > On Mon, Jan 1, 2024 at 2:59 PM 钟居哲 <juzhe.zhong@rivai.ai> wrote:
> > >
> > > This is Ok from my side.
> > > But before commit this patch, I think we need this patch first:
> > > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
> > >
> > > I will be back to work so I will take a look at other patches today.
> >
> >
> > Note I hate it. It would be better if you use something like `%^' (see
> > `~` for an example of how that works) instead of hacking
> > riscv_asm_output_opcode really. In fact that is how other targets
> > implement this kind of things.
> >
> > Thanks,
> > Andrew PInski
> >
> > > ________________________________
> > > juzhe.zhong@rivai.ai
> > >
> > >
> > > From: Jeff Law
> > > Date: 2024-01-01 01:43
> > > To: Jun Sha (Joshua); gcc-patches
> > > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
> > > Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> > >
> > >
> > > On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> > > > This patch adds th. prefix to all XTheadVector instructions by
> > > > implementing new assembly output functions. We only check the
> > > > prefix is 'v', so that no extra attribute is needed.
> > > >
> > > > gcc/ChangeLog:
> > > >
> > > > * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> > > > New function to add assembler insn code prefix/suffix.
> > > > * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> > > > * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> > > >
> > > > Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> > > > Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> > > > Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > > > ---
> > > >   gcc/config/riscv/riscv-protos.h                    |  1 +
> > > >   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
> > > >   gcc/config/riscv/riscv.h                           |  4 ++++
> > > >   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
> > > >   4 files changed, 31 insertions(+)
> > > >   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> > > >
> > > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> > > > index 31049ef7523..5ea54b45703 100644
> > > > --- a/gcc/config/riscv/riscv-protos.h
> > > > +++ b/gcc/config/riscv/riscv-protos.h
> > > > @@ -102,6 +102,7 @@ struct riscv_address_info {
> > > >   };
> > > >
> > > >   /* Routines implemented in riscv.cc.  */
> > > > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
> > > >   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
> > > >   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
> > > >   extern int riscv_float_const_rtx_index_for_fli (rtx);
> > > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > > > index 0d1cbc5cb5f..ea1d59d9cf2 100644
> > > > --- a/gcc/config/riscv/riscv.cc
> > > > +++ b/gcc/config/riscv/riscv.cc
> > > > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
> > > >     return lmul;
> > > >   }
> > > >
> > > > +/* Define ASM_OUTPUT_OPCODE to do anything special before
> > > > +   emitting an opcode.  */
> > > > +const char *
> > > > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> > > > +{
> > > > +  /* We need to add th. prefix to all the xtheadvector
> > > > +     insturctions here.*/
> > > > +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> > > > +      p[0] == 'v')
> > > > +    fputs ("th.", asm_out_file);
> > > > +
> > > > +  return p;
> > > Just a formatting nit. The GNU standards break lines before the
> > > operator, not after.  So
> > >    if (TARGET_XTHEADVECTOR
> > >        && current_output_insn != NULL
> > >        && p[0] == 'v')
> > >
> > > Note that current_output_insn is "extern rtx_insn *", so use NULL, not
> > > NULL_RTX.
> > >
> > > Neither of these nits require a new version for review.  Just fix them.
> > >
> > > If Juzhe is fine with this, so am I.  We can refine it if necessary later.
> > >
> > > jeff
> > >
> >
>
joshua Jan. 4, 2024, 9:15 a.m. UTC | #9 
Hi Juzhe,

So is the following patch that this patch relies on OK to commit?
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html

Joshua




------------------------------------------------------------------
发件人：钟居哲 <juzhe.zhong@rivai.ai>
发送时间：2024年1月2日(星期二) 06:57
收件人：Jeff Law<jeffreyalaw@gmail.com>; "cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄　送："jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "Christoph Müllner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; Cooper Qu<cooper.qu@linux.alibaba.com>
主　题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.


This is Ok from my side.
But before commit this patch, I think we need this patch first:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html 


I will be back to work so I will take a look at other patches today.
juzhe.zhong@rivai.ai

 
From: Jeff Law
Date: 2024-01-01 01:43
To: Jun Sha (Joshua); gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

 
 
On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> This patch adds th. prefix to all XTheadVector instructions by
> implementing new assembly output functions. We only check the
> prefix is 'v', so that no extra attribute is needed.
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> 	New function to add assembler insn code prefix/suffix.
> 	* config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> 	* config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> 
> Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>   gcc/config/riscv/riscv-protos.h                    |  1 +
>   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
>   gcc/config/riscv/riscv.h                           |  4 ++++
>   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
>   4 files changed, 31 insertions(+)
>   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> 
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 31049ef7523..5ea54b45703 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -102,6 +102,7 @@ struct riscv_address_info {
>   };
>   
>   /* Routines implemented in riscv.cc.  */
> +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
>   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
>   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
>   extern int riscv_float_const_rtx_index_for_fli (rtx);
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 0d1cbc5cb5f..ea1d59d9cf2 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
>     return lmul;
>   }
>   
> +/* Define ASM_OUTPUT_OPCODE to do anything special before
> +   emitting an opcode.  */
> +const char *
> +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> +{
> +  /* We need to add th. prefix to all the xtheadvector
> +     insturctions here.*/
> +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> +      p[0] == 'v')
> +    fputs ("th.", asm_out_file);
> +
> +  return p;
Just a formatting nit. The GNU standards break lines before the 
operator, not after.  So
   if (TARGET_XTHEADVECTOR
       && current_output_insn != NULL
       && p[0] == 'v')
 
Note that current_output_insn is "extern rtx_insn *", so use NULL, not 
NULL_RTX.
 
Neither of these nits require a new version for review.  Just fix them.
 
If Juzhe is fine with this, so am I.  We can refine it if necessary later.
 
jeff
juzhe.zhong@rivai.ai Jan. 4, 2024, 9:18 a.m. UTC | #10 
\ No newline at end of file
Each file needs newline.

I am not able to review arch stuff. This needs kito.

Besides, Andrew Pinski want us defer theadvector to GCC-15.

I have no strong opinion here.



juzhe.zhong@rivai.ai
 
发件人： joshua
发送时间： 2024-01-04 17:15
收件人： 钟居哲; Jeff Law; gcc-patches
抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; Cooper Qu
主题： Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
Hi Juzhe,
 
So is the following patch that this patch relies on OK to commit?
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
 
Joshua
 
 
 
 
------------------------------------------------------------------
发件人：钟居哲 <juzhe.zhong@rivai.ai>
发送时间：2024年1月2日(星期二) 06:57
收件人：Jeff Law<jeffreyalaw@gmail.com>; "cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄　送："jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "Christoph Müllner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; Cooper Qu<cooper.qu@linux.alibaba.com>
主　题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
 
 
This is Ok from my side.
But before commit this patch, I think we need this patch first:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html 
 
 
I will be back to work so I will take a look at other patches today.
juzhe.zhong@rivai.ai
 
 
From: Jeff Law
Date: 2024-01-01 01:43
To: Jun Sha (Joshua); gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
 
 
 
On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> This patch adds th. prefix to all XTheadVector instructions by
> implementing new assembly output functions. We only check the
> prefix is 'v', so that no extra attribute is needed.
> 
> gcc/ChangeLog:
> 
> * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> New function to add assembler insn code prefix/suffix.
> * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> 
> Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>   gcc/config/riscv/riscv-protos.h                    |  1 +
>   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
>   gcc/config/riscv/riscv.h                           |  4 ++++
>   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
>   4 files changed, 31 insertions(+)
>   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> 
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 31049ef7523..5ea54b45703 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -102,6 +102,7 @@ struct riscv_address_info {
>   };
>   
>   /* Routines implemented in riscv.cc.  */
> +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
>   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
>   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
>   extern int riscv_float_const_rtx_index_for_fli (rtx);
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 0d1cbc5cb5f..ea1d59d9cf2 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
>     return lmul;
>   }
>   
> +/* Define ASM_OUTPUT_OPCODE to do anything special before
> +   emitting an opcode.  */
> +const char *
> +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> +{
> +  /* We need to add th. prefix to all the xtheadvector
> +     insturctions here.*/
> +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> +      p[0] == 'v')
> +    fputs ("th.", asm_out_file);
> +
> +  return p;
Just a formatting nit. The GNU standards break lines before the 
operator, not after.  So
   if (TARGET_XTHEADVECTOR
       && current_output_insn != NULL
       && p[0] == 'v')
 
Note that current_output_insn is "extern rtx_insn *", so use NULL, not 
NULL_RTX.
 
Neither of these nits require a new version for review.  Just fix them.
 
If Juzhe is fine with this, so am I.  We can refine it if necessary later.
 
jeff
Christoph Müllner Jan. 4, 2024, 10:04 a.m. UTC | #11 
On Thu, Jan 4, 2024 at 10:18 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> \ No newline at end of file
>
> Each file needs newline.
>
> I am not able to review arch stuff. This needs kito.
>
> Besides, Andrew Pinski want us defer theadvector to GCC-15.

Maybe I misread this (sorry if so), but I though that was answered by Kito here:
  https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641723.html




>
> I have no strong opinion here.
>
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> 发件人： joshua
> 发送时间： 2024-01-04 17:15
> 收件人： 钟居哲; Jeff Law; gcc-patches
> 抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; Cooper Qu
> 主题： Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> Hi Juzhe,
>
> So is the following patch that this patch relies on OK to commit?
> https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
>
> Joshua
>
>
>
>
> ------------------------------------------------------------------
> 发件人：钟居哲 <juzhe.zhong@rivai.ai>
> 发送时间：2024年1月2日(星期二) 06:57
> 收件人：Jeff Law<jeffreyalaw@gmail.com>; "cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
> 抄　送："jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "Christoph Müllner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; Cooper Qu<cooper.qu@linux.alibaba.com>
> 主　题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
>
>
> This is Ok from my side.
> But before commit this patch, I think we need this patch first:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
>
>
> I will be back to work so I will take a look at other patches today.
> juzhe.zhong@rivai.ai
>
>
> From: Jeff Law
> Date: 2024-01-01 01:43
> To: Jun Sha (Joshua); gcc-patches
> CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
> Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
>
>
>
> On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> > This patch adds th. prefix to all XTheadVector instructions by
> > implementing new assembly output functions. We only check the
> > prefix is 'v', so that no extra attribute is needed.
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> > New function to add assembler insn code prefix/suffix.
> > * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> > * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> >
> > Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> > Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> > Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> >   gcc/config/riscv/riscv-protos.h                    |  1 +
> >   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
> >   gcc/config/riscv/riscv.h                           |  4 ++++
> >   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
> >   4 files changed, 31 insertions(+)
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> >
> > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> > index 31049ef7523..5ea54b45703 100644
> > --- a/gcc/config/riscv/riscv-protos.h
> > +++ b/gcc/config/riscv/riscv-protos.h
> > @@ -102,6 +102,7 @@ struct riscv_address_info {
> >   };
> >
> >   /* Routines implemented in riscv.cc.  */
> > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
> >   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
> >   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
> >   extern int riscv_float_const_rtx_index_for_fli (rtx);
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 0d1cbc5cb5f..ea1d59d9cf2 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
> >     return lmul;
> >   }
> >
> > +/* Define ASM_OUTPUT_OPCODE to do anything special before
> > +   emitting an opcode.  */
> > +const char *
> > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> > +{
> > +  /* We need to add th. prefix to all the xtheadvector
> > +     insturctions here.*/
> > +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> > +      p[0] == 'v')
> > +    fputs ("th.", asm_out_file);
> > +
> > +  return p;
> Just a formatting nit. The GNU standards break lines before the
> operator, not after.  So
>    if (TARGET_XTHEADVECTOR
>        && current_output_insn != NULL
>        && p[0] == 'v')
>
> Note that current_output_insn is "extern rtx_insn *", so use NULL, not
> NULL_RTX.
>
> Neither of these nits require a new version for review.  Just fix them.
>
> If Juzhe is fine with this, so am I.  We can refine it if necessary later.
>
> jeff
>
>
>
joshua Jan. 8, 2024, 2:11 a.m. UTC | #12 
Hi Juzhe,

Stage 3 will close today and there are still some patches that
haven't been reviewed left. 
So is it possible to get xtheadvector merged in GCC-14?
We emailed Kito regarding this, but haven't got any reply yet.

Joshua






------------------------------------------------------------------
发件人：juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
发送时间：2024年1月4日(星期四) 17:18
收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; jeffreyalaw<jeffreyalaw@gmail.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄　送：Jim Wilson<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "christoph.muellner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; "cooper.qu"<cooper.qu@linux.alibaba.com>
主　题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.


\ No newline at end of file
Each file needs newline.


I am not able to review arch stuff. This needs kito.


Besides, Andrew Pinski want us defer theadvector to GCC-15.


I have no strong opinion here.


juzhe.zhong@rivai.ai

 
发件人： joshua
发送时间： 2024-01-04 17:15
收件人： 钟居哲; Jeff Law; gcc-patches
抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; Cooper Qu
主题： Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

Hi Juzhe,
 
So is the following patch that this patch relies on OK to commit?
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
 
Joshua
 
 
 
 
------------------------------------------------------------------
发件人：钟居哲 <juzhe.zhong@rivai.ai>
发送时间：2024年1月2日(星期二) 06:57
收件人：Jeff Law<jeffreyalaw@gmail.com>; "cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄　送："jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "Christoph Müllner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; Cooper Qu<cooper.qu@linux.alibaba.com>
主　题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
 
 
This is Ok from my side.
But before commit this patch, I think we need this patch first:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html 
 
 
I will be back to work so I will take a look at other patches today.
juzhe.zhong@rivai.ai
 
 
From: Jeff Law
Date: 2024-01-01 01:43
To: Jun Sha (Joshua); gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
 
 
 
On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> This patch adds th. prefix to all XTheadVector instructions by
> implementing new assembly output functions. We only check the
> prefix is 'v', so that no extra attribute is needed.
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> 	New function to add assembler insn code prefix/suffix.
> 	* config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> 	* config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> 
> Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>   gcc/config/riscv/riscv-protos.h                    |  1 +
>   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
>   gcc/config/riscv/riscv.h                           |  4 ++++
>   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
>   4 files changed, 31 insertions(+)
>   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> 
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 31049ef7523..5ea54b45703 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -102,6 +102,7 @@ struct riscv_address_info {
>   };
>   
>   /* Routines implemented in riscv.cc.  */
> +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
>   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
>   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
>   extern int riscv_float_const_rtx_index_for_fli (rtx);
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 0d1cbc5cb5f..ea1d59d9cf2 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
>     return lmul;
>   }
>   
> +/* Define ASM_OUTPUT_OPCODE to do anything special before
> +   emitting an opcode.  */
> +const char *
> +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> +{
> +  /* We need to add th. prefix to all the xtheadvector
> +     insturctions here.*/
> +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> +      p[0] == 'v')
> +    fputs ("th.", asm_out_file);
> +
> +  return p;
Just a formatting nit. The GNU standards break lines before the 
operator, not after.  So
   if (TARGET_XTHEADVECTOR
       && current_output_insn != NULL
       && p[0] == 'v')
 
Note that current_output_insn is "extern rtx_insn *", so use NULL, not 
NULL_RTX.
 
Neither of these nits require a new version for review.  Just fix them.
 
If Juzhe is fine with this, so am I.  We can refine it if necessary later.
 
jeff
Kito Cheng Jan. 8, 2024, 3:06 a.m. UTC | #13 
I am ok with merging this for GCC 14, as we discussed several times in
the RISC-V GCC sync up meeting, I think at least we reach consensus
among Jeff Law, Palmer Dabbelt and me.

But please be careful: don't break anything for standard vector stuff.

On Mon, Jan 8, 2024 at 10:11 AM joshua <cooper.joshua@linux.alibaba.com> wrote:
>
> Hi Juzhe,
>
> Stage 3 will close today and there are still some patches that
> haven't been reviewed left.
> So is it possible to get xtheadvector merged in GCC-14?
> We emailed Kito regarding this, but haven't got any reply yet.
>
> Joshua
>
>
>
>
>
>
> ------------------------------------------------------------------
> 发件人：juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
> 发送时间：2024年1月4日(星期四) 17:18
> 收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; jeffreyalaw<jeffreyalaw@gmail.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
> 抄　送：Jim Wilson<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "christoph.muellner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; "cooper.qu"<cooper.qu@linux.alibaba.com>
> 主　题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
>
>
> \ No newline at end of file
> Each file needs newline.
>
>
> I am not able to review arch stuff. This needs kito.
>
>
> Besides, Andrew Pinski want us defer theadvector to GCC-15.
>
>
> I have no strong opinion here.
>
>
> juzhe.zhong@rivai.ai
>
>
> 发件人： joshua
> 发送时间： 2024-01-04 17:15
> 收件人： 钟居哲; Jeff Law; gcc-patches
> 抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; Cooper Qu
> 主题： Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
>
> Hi Juzhe,
>
> So is the following patch that this patch relies on OK to commit?
> https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
>
> Joshua
>
>
>
>
> ------------------------------------------------------------------
> 发件人：钟居哲 <juzhe.zhong@rivai.ai>
> 发送时间：2024年1月2日(星期二) 06:57
> 收件人：Jeff Law<jeffreyalaw@gmail.com>; "cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
> 抄　送："jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "Christoph Müllner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; Cooper Qu<cooper.qu@linux.alibaba.com>
> 主　题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
>
>
> This is Ok from my side.
> But before commit this patch, I think we need this patch first:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
>
>
> I will be back to work so I will take a look at other patches today.
> juzhe.zhong@rivai.ai
>
>
> From: Jeff Law
> Date: 2024-01-01 01:43
> To: Jun Sha (Joshua); gcc-patches
> CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
> Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
>
>
>
> On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> > This patch adds th. prefix to all XTheadVector instructions by
> > implementing new assembly output functions. We only check the
> > prefix is 'v', so that no extra attribute is needed.
> >
> > gcc/ChangeLog:
> >
> >       * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> >       New function to add assembler insn code prefix/suffix.
> >       * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> >       * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> >
> > Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> > Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> > Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> >   gcc/config/riscv/riscv-protos.h                    |  1 +
> >   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
> >   gcc/config/riscv/riscv.h                           |  4 ++++
> >   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
> >   4 files changed, 31 insertions(+)
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> >
> > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> > index 31049ef7523..5ea54b45703 100644
> > --- a/gcc/config/riscv/riscv-protos.h
> > +++ b/gcc/config/riscv/riscv-protos.h
> > @@ -102,6 +102,7 @@ struct riscv_address_info {
> >   };
> >
> >   /* Routines implemented in riscv.cc.  */
> > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
> >   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
> >   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
> >   extern int riscv_float_const_rtx_index_for_fli (rtx);
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 0d1cbc5cb5f..ea1d59d9cf2 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
> >     return lmul;
> >   }
> >
> > +/* Define ASM_OUTPUT_OPCODE to do anything special before
> > +   emitting an opcode.  */
> > +const char *
> > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> > +{
> > +  /* We need to add th. prefix to all the xtheadvector
> > +     insturctions here.*/
> > +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> > +      p[0] == 'v')
> > +    fputs ("th.", asm_out_file);
> > +
> > +  return p;
> Just a formatting nit. The GNU standards break lines before the
> operator, not after.  So
>    if (TARGET_XTHEADVECTOR
>        && current_output_insn != NULL
>        && p[0] == 'v')
>
> Note that current_output_insn is "extern rtx_insn *", so use NULL, not
> NULL_RTX.
>
> Neither of these nits require a new version for review.  Just fix them.
>
> If Juzhe is fine with this, so am I.  We can refine it if necessary later.
>
> jeff
>
>
>
>
>
joshua Jan. 8, 2024, 3:17 a.m. UTC | #14 
Hi Kito,

Thank you for your support.
So even during stage 4, we can merge this for GCC 14?





------------------------------------------------------------------
发件人：Kito Cheng <kito.cheng@gmail.com>
发送时间：2024年1月8日(星期一) 11:06
收件人：joshua<cooper.joshua@linux.alibaba.com>
抄　送："juzhe.zhong@rivai.ai"<juzhe.zhong@rivai.ai>; jeffreyalaw<jeffreyalaw@gmail.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>; Jim Wilson<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "christoph.muellner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; "cooper.qu"<cooper.qu@linux.alibaba.com>
主　题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.


I am ok with merging this for GCC 14, as we discussed several times in
the RISC-V GCC sync up meeting, I think at least we reach consensus
among Jeff Law, Palmer Dabbelt and me.

But please be careful: don't break anything for standard vector stuff.

On Mon, Jan 8, 2024 at 10:11 AM joshua <cooper.joshua@linux.alibaba.com> wrote:
>
> Hi Juzhe,
>
> Stage 3 will close today and there are still some patches that
> haven't been reviewed left.
> So is it possible to get xtheadvector merged in GCC-14?
> We emailed Kito regarding this, but haven't got any reply yet.
>
> Joshua
>
>
>
>
>
>
> ------------------------------------------------------------------
> 发件人：juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
> 发送时间：2024年1月4日(星期四) 17:18
> 收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; jeffreyalaw<jeffreyalaw@gmail.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
> 抄 送：Jim Wilson<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "christoph.muellner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; "cooper.qu"<cooper.qu@linux.alibaba.com>
> 主 题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
>
>
> \ No newline at end of file
> Each file needs newline.
>
>
> I am not able to review arch stuff. This needs kito.
>
>
> Besides, Andrew Pinski want us defer theadvector to GCC-15.
>
>
> I have no strong opinion here.
>
>
> juzhe.zhong@rivai.ai
>
>
> 发件人： joshua
> 发送时间： 2024-01-04 17:15
> 收件人： 钟居哲; Jeff Law; gcc-patches
> 抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; Cooper Qu
> 主题： Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
>
> Hi Juzhe,
>
> So is the following patch that this patch relies on OK to commit?
> https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
>
> Joshua
>
>
>
>
> ------------------------------------------------------------------
> 发件人：钟居哲 <juzhe.zhong@rivai.ai>
> 发送时间：2024年1月2日(星期二) 06:57
> 收件人：Jeff Law<jeffreyalaw@gmail.com>; "cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
> 抄 送："jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "Christoph Müllner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; Cooper Qu<cooper.qu@linux.alibaba.com>
> 主 题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
>
>
> This is Ok from my side.
> But before commit this patch, I think we need this patch first:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
>
>
> I will be back to work so I will take a look at other patches today.
> juzhe.zhong@rivai.ai
>
>
> From: Jeff Law
> Date: 2024-01-01 01:43
> To: Jun Sha (Joshua); gcc-patches
> CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
> Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
>
>
>
> On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> > This patch adds th. prefix to all XTheadVector instructions by
> > implementing new assembly output functions. We only check the
> > prefix is 'v', so that no extra attribute is needed.
> >
> > gcc/ChangeLog:
> >
> >       * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> >       New function to add assembler insn code prefix/suffix.
> >       * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> >       * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> >
> > Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> > Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> > Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> >   gcc/config/riscv/riscv-protos.h                    |  1 +
> >   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
> >   gcc/config/riscv/riscv.h                           |  4 ++++
> >   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
> >   4 files changed, 31 insertions(+)
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> >
> > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> > index 31049ef7523..5ea54b45703 100644
> > --- a/gcc/config/riscv/riscv-protos.h
> > +++ b/gcc/config/riscv/riscv-protos.h
> > @@ -102,6 +102,7 @@ struct riscv_address_info {
> >   };
> >
> >   /* Routines implemented in riscv.cc.  */
> > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
> >   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
> >   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
> >   extern int riscv_float_const_rtx_index_for_fli (rtx);
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 0d1cbc5cb5f..ea1d59d9cf2 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
> >     return lmul;
> >   }
> >
> > +/* Define ASM_OUTPUT_OPCODE to do anything special before
> > +   emitting an opcode.  */
> > +const char *
> > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> > +{
> > +  /* We need to add th. prefix to all the xtheadvector
> > +     insturctions here.*/
> > +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> > +      p[0] == 'v')
> > +    fputs ("th.", asm_out_file);
> > +
> > +  return p;
> Just a formatting nit. The GNU standards break lines before the
> operator, not after.  So
>    if (TARGET_XTHEADVECTOR
>        && current_output_insn != NULL
>        && p[0] == 'v')
>
> Note that current_output_insn is "extern rtx_insn *", so use NULL, not
> NULL_RTX.
>
> Neither of these nits require a new version for review.  Just fix them.
>
> If Juzhe is fine with this, so am I.  We can refine it if necessary later.
>
> jeff
>
>
>
>
>
Kito Cheng Jan. 8, 2024, 3:40 a.m. UTC | #15 
It depends on the timing when you send out the v1 patch to the mailing
list, not the timing of when to merge, but of course it's case by
case, I would say no IF it's still not ready when time is the end of
Feb for this kind of big patch set.

On Mon, Jan 8, 2024 at 11:17 AM joshua <cooper.joshua@linux.alibaba.com> wrote:
>
> Hi Kito,
>
> Thank you for your support.
> So even during stage 4, we can merge this for GCC 14?
>
>
>
>
>
> ------------------------------------------------------------------
> 发件人：Kito Cheng <kito.cheng@gmail.com>
> 发送时间：2024年1月8日(星期一) 11:06
> 收件人：joshua<cooper.joshua@linux.alibaba.com>
> 抄　送："juzhe.zhong@rivai.ai"<juzhe.zhong@rivai.ai>; jeffreyalaw<jeffreyalaw@gmail.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>; Jim Wilson<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "christoph.muellner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; "cooper.qu"<cooper.qu@linux.alibaba.com>
> 主　题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
>
>
> I am ok with merging this for GCC 14, as we discussed several times in
> the RISC-V GCC sync up meeting, I think at least we reach consensus
> among Jeff Law, Palmer Dabbelt and me.
>
> But please be careful: don't break anything for standard vector stuff.
>
> On Mon, Jan 8, 2024 at 10:11 AM joshua <cooper.joshua@linux.alibaba.com> wrote:
> >
> > Hi Juzhe,
> >
> > Stage 3 will close today and there are still some patches that
> > haven't been reviewed left.
> > So is it possible to get xtheadvector merged in GCC-14?
> > We emailed Kito regarding this, but haven't got any reply yet.
> >
> > Joshua
> >
> >
> >
> >
> >
> >
> > ------------------------------------------------------------------
> > 发件人：juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
> > 发送时间：2024年1月4日(星期四) 17:18
> > 收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; jeffreyalaw<jeffreyalaw@gmail.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
> > 抄 送：Jim Wilson<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "christoph.muellner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; "cooper.qu"<cooper.qu@linux.alibaba.com>
> > 主 题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> >
> >
> > \ No newline at end of file
> > Each file needs newline.
> >
> >
> > I am not able to review arch stuff. This needs kito.
> >
> >
> > Besides, Andrew Pinski want us defer theadvector to GCC-15.
> >
> >
> > I have no strong opinion here.
> >
> >
> > juzhe.zhong@rivai.ai
> >
> >
> > 发件人： joshua
> > 发送时间： 2024-01-04 17:15
> > 收件人： 钟居哲; Jeff Law; gcc-patches
> > 抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; Cooper Qu
> > 主题： Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> >
> > Hi Juzhe,
> >
> > So is the following patch that this patch relies on OK to commit?
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
> >
> > Joshua
> >
> >
> >
> >
> > ------------------------------------------------------------------
> > 发件人：钟居哲 <juzhe.zhong@rivai.ai>
> > 发送时间：2024年1月2日(星期二) 06:57
> > 收件人：Jeff Law<jeffreyalaw@gmail.com>; "cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
> > 抄 送："jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "Christoph Müllner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; Cooper Qu<cooper.qu@linux.alibaba.com>
> > 主 题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> >
> >
> > This is Ok from my side.
> > But before commit this patch, I think we need this patch first:
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
> >
> >
> > I will be back to work so I will take a look at other patches today.
> > juzhe.zhong@rivai.ai
> >
> >
> > From: Jeff Law
> > Date: 2024-01-01 01:43
> > To: Jun Sha (Joshua); gcc-patches
> > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
> > Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> >
> >
> >
> > On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> > > This patch adds th. prefix to all XTheadVector instructions by
> > > implementing new assembly output functions. We only check the
> > > prefix is 'v', so that no extra attribute is needed.
> > >
> > > gcc/ChangeLog:
> > >
> > >       * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> > >       New function to add assembler insn code prefix/suffix.
> > >       * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> > >       * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> > >
> > > Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> > > Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> > > Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > > ---
> > >   gcc/config/riscv/riscv-protos.h                    |  1 +
> > >   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
> > >   gcc/config/riscv/riscv.h                           |  4 ++++
> > >   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
> > >   4 files changed, 31 insertions(+)
> > >   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> > >
> > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> > > index 31049ef7523..5ea54b45703 100644
> > > --- a/gcc/config/riscv/riscv-protos.h
> > > +++ b/gcc/config/riscv/riscv-protos.h
> > > @@ -102,6 +102,7 @@ struct riscv_address_info {
> > >   };
> > >
> > >   /* Routines implemented in riscv.cc.  */
> > > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
> > >   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
> > >   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
> > >   extern int riscv_float_const_rtx_index_for_fli (rtx);
> > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > > index 0d1cbc5cb5f..ea1d59d9cf2 100644
> > > --- a/gcc/config/riscv/riscv.cc
> > > +++ b/gcc/config/riscv/riscv.cc
> > > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
> > >     return lmul;
> > >   }
> > >
> > > +/* Define ASM_OUTPUT_OPCODE to do anything special before
> > > +   emitting an opcode.  */
> > > +const char *
> > > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> > > +{
> > > +  /* We need to add th. prefix to all the xtheadvector
> > > +     insturctions here.*/
> > > +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> > > +      p[0] == 'v')
> > > +    fputs ("th.", asm_out_file);
> > > +
> > > +  return p;
> > Just a formatting nit. The GNU standards break lines before the
> > operator, not after.  So
> >    if (TARGET_XTHEADVECTOR
> >        && current_output_insn != NULL
> >        && p[0] == 'v')
> >
> > Note that current_output_insn is "extern rtx_insn *", so use NULL, not
> > NULL_RTX.
> >
> > Neither of these nits require a new version for review.  Just fix them.
> >
> > If Juzhe is fine with this, so am I.  We can refine it if necessary later.
> >
> > jeff
> >
> >
> >
> >
> >
joshua Jan. 10, 2024, 3:01 a.m. UTC | #16 
Hi Kito,

Thank you for your support again.
I believe we can get all our xtheadvector patches
ready before the end of Feb.

May I please ping the arch patch again?
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641801.html
This is the patch that all the following patches rely on.

Joshua






------------------------------------------------------------------
发件人：Kito Cheng <kito.cheng@gmail.com>
发送时间：2024年1月8日(星期一) 11:40
收件人：joshua<cooper.joshua@linux.alibaba.com>
抄　送："juzhe.zhong@rivai.ai"<juzhe.zhong@rivai.ai>; jeffreyalaw<jeffreyalaw@gmail.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>; Jim Wilson<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "christoph.muellner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; "cooper.qu"<cooper.qu@linux.alibaba.com>
主　题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.


It depends on the timing when you send out the v1 patch to the mailing
list, not the timing of when to merge, but of course it's case by
case, I would say no IF it's still not ready when time is the end of
Feb for this kind of big patch set.

On Mon, Jan 8, 2024 at 11:17 AM joshua <cooper.joshua@linux.alibaba.com> wrote:
>
> Hi Kito,
>
> Thank you for your support.
> So even during stage 4, we can merge this for GCC 14?
>
>
>
>
>
> ------------------------------------------------------------------
> 发件人：Kito Cheng <kito.cheng@gmail.com>
> 发送时间：2024年1月8日(星期一) 11:06
> 收件人：joshua<cooper.joshua@linux.alibaba.com>
> 抄 送："juzhe.zhong@rivai.ai"<juzhe.zhong@rivai.ai>; jeffreyalaw<jeffreyalaw@gmail.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>; Jim Wilson<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "christoph.muellner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; "cooper.qu"<cooper.qu@linux.alibaba.com>
> 主 题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
>
>
> I am ok with merging this for GCC 14, as we discussed several times in
> the RISC-V GCC sync up meeting, I think at least we reach consensus
> among Jeff Law, Palmer Dabbelt and me.
>
> But please be careful: don't break anything for standard vector stuff.
>
> On Mon, Jan 8, 2024 at 10:11 AM joshua <cooper.joshua@linux.alibaba.com> wrote:
> >
> > Hi Juzhe,
> >
> > Stage 3 will close today and there are still some patches that
> > haven't been reviewed left.
> > So is it possible to get xtheadvector merged in GCC-14?
> > We emailed Kito regarding this, but haven't got any reply yet.
> >
> > Joshua
> >
> >
> >
> >
> >
> >
> > ------------------------------------------------------------------
> > 发件人：juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
> > 发送时间：2024年1月4日(星期四) 17:18
> > 收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; jeffreyalaw<jeffreyalaw@gmail.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
> > 抄 送：Jim Wilson<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "christoph.muellner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; "cooper.qu"<cooper.qu@linux.alibaba.com>
> > 主 题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> >
> >
> > \ No newline at end of file
> > Each file needs newline.
> >
> >
> > I am not able to review arch stuff. This needs kito.
> >
> >
> > Besides, Andrew Pinski want us defer theadvector to GCC-15.
> >
> >
> > I have no strong opinion here.
> >
> >
> > juzhe.zhong@rivai.ai
> >
> >
> > 发件人： joshua
> > 发送时间： 2024-01-04 17:15
> > 收件人： 钟居哲; Jeff Law; gcc-patches
> > 抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; Cooper Qu
> > 主题： Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> >
> > Hi Juzhe,
> >
> > So is the following patch that this patch relies on OK to commit?
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
> >
> > Joshua
> >
> >
> >
> >
> > ------------------------------------------------------------------
> > 发件人：钟居哲 <juzhe.zhong@rivai.ai>
> > 发送时间：2024年1月2日(星期二) 06:57
> > 收件人：Jeff Law<jeffreyalaw@gmail.com>; "cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
> > 抄 送："jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "Christoph Müllner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; Cooper Qu<cooper.qu@linux.alibaba.com>
> > 主 题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> >
> >
> > This is Ok from my side.
> > But before commit this patch, I think we need this patch first:
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
> >
> >
> > I will be back to work so I will take a look at other patches today.
> > juzhe.zhong@rivai.ai
> >
> >
> > From: Jeff Law
> > Date: 2024-01-01 01:43
> > To: Jun Sha (Joshua); gcc-patches
> > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
> > Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
> >
> >
> >
> > On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> > > This patch adds th. prefix to all XTheadVector instructions by
> > > implementing new assembly output functions. We only check the
> > > prefix is 'v', so that no extra attribute is needed.
> > >
> > > gcc/ChangeLog:
> > >
> > >       * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> > >       New function to add assembler insn code prefix/suffix.
> > >       * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> > >       * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> > >
> > > Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> > > Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> > > Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > > ---
> > >   gcc/config/riscv/riscv-protos.h                    |  1 +
> > >   gcc/config/riscv/riscv.cc                          | 14 ++++++++++++++
> > >   gcc/config/riscv/riscv.h                           |  4 ++++
> > >   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 ++++++++++++
> > >   4 files changed, 31 insertions(+)
> > >   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> > >
> > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> > > index 31049ef7523..5ea54b45703 100644
> > > --- a/gcc/config/riscv/riscv-protos.h
> > > +++ b/gcc/config/riscv/riscv-protos.h
> > > @@ -102,6 +102,7 @@ struct riscv_address_info {
> > >   };
> > >
> > >   /* Routines implemented in riscv.cc.  */
> > > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
> > >   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
> > >   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
> > >   extern int riscv_float_const_rtx_index_for_fli (rtx);
> > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > > index 0d1cbc5cb5f..ea1d59d9cf2 100644
> > > --- a/gcc/config/riscv/riscv.cc
> > > +++ b/gcc/config/riscv/riscv.cc
> > > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
> > >     return lmul;
> > >   }
> > >
> > > +/* Define ASM_OUTPUT_OPCODE to do anything special before
> > > +   emitting an opcode.  */
> > > +const char *
> > > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> > > +{
> > > +  /* We need to add th. prefix to all the xtheadvector
> > > +     insturctions here.*/
> > > +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> > > +      p[0] == 'v')
> > > +    fputs ("th.", asm_out_file);
> > > +
> > > +  return p;
> > Just a formatting nit. The GNU standards break lines before the
> > operator, not after.  So
> >    if (TARGET_XTHEADVECTOR
> >        && current_output_insn != NULL
> >        && p[0] == 'v')
> >
> > Note that current_output_insn is "extern rtx_insn *", so use NULL, not
> > NULL_RTX.
> >
> > Neither of these nits require a new version for review.  Just fix them.
> >
> > If Juzhe is fine with this, so am I.  We can refine it if necessary later.
> >
> > jeff
> >
> >
> >
> >
> >
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 31049ef7523..5ea54b45703 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -102,6 +102,7 @@  struct riscv_address_info {
 };
 
 /* Routines implemented in riscv.cc.  */
+extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
 extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
 extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
 extern int riscv_float_const_rtx_index_for_fli (rtx);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0d1cbc5cb5f..ea1d59d9cf2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5636,6 +5636,20 @@  riscv_get_v_regno_alignment (machine_mode mode)
   return lmul;
 }
 
+/* Define ASM_OUTPUT_OPCODE to do anything special before
+   emitting an opcode.  */
+const char *
+riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
+{
+  /* We need to add th. prefix to all the xtheadvector
+     insturctions here.*/
+  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
+      p[0] == 'v')
+    fputs ("th.", asm_out_file);
+
+  return p;
+}
+
 /* Implement TARGET_PRINT_OPERAND.  The RISCV-specific operand codes are:
 
    'h'	Print the high-part relocation associated with OP, after stripping
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 6df9ec73c5e..c33361a254d 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -826,6 +826,10 @@  extern enum riscv_cc get_riscv_cc (const rtx use);
       asm_fprintf ((FILE), "%U%s", (NAME));				\
   } while (0)
 
+#undef ASM_OUTPUT_OPCODE
+#define ASM_OUTPUT_OPCODE(STREAM, PTR)	\
+  (PTR) = riscv_asm_output_opcode(STREAM, PTR)
+
 #define JUMP_TABLES_IN_TEXT_SECTION 0
 #define CASE_VECTOR_MODE SImode
 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
new file mode 100644
index 00000000000..eee727ef6b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
@@ -0,0 +1,12 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32 -O0" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+prefix (vint32m1_t vx, vint32m1_t vy, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (vx, vy, vl);
+}
+
+/* { dg-final { scan-assembler {\mth\.v\M} } } */