diff mbox series

testsuite: Fix dump checks under different riscv-sim for RVV.

Message ID 20231219053000.2741-1-xuli1@eswincomputing.com
State New
Headers show
Series testsuite: Fix dump checks under different riscv-sim for RVV. | expand

Commit Message

Li Xu Dec. 19, 2023, 5:30 a.m. UTC 
From: xuli <xuli1@eswincomputing.com>

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/cpymem-1.c: Fix checks under medany.
	* gcc.target/riscv/rvv/base/cpymem-strategy-3.c: Fix checks.
	* gcc.target/riscv/rvv/base/cpymem-strategy-4.c: Ditto.
---
 .../gcc.target/riscv/rvv/base/cpymem-1.c      | 23 +++++++++++++++++--
 .../riscv/rvv/base/cpymem-strategy-3.c        |  3 ++-
 .../riscv/rvv/base/cpymem-strategy-4.c        |  3 ++-
 3 files changed, 25 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
index ccde7575051..9efe258c99a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
@@ -85,15 +85,34 @@  void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)
 */
 
 /*
-** f3: { target { any-opts "-mcmodel=medany" } }
+** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-preference=fixed-vlmax" } } }
+**        lla\s+[ta][0-7],a_a
 **        lla\s+[ta][0-7],a_b
-**        vsetivli\s+zero,16,e32,m4,ta,ma
+**        vsetivli\s+zero,16,e32,m8,ta,ma
+**        vle32.v\s+v\d+,0\([ta][0-7]\)
+**        vse32\.v\s+v\d+,0\([ta][0-7]\)
+**        ret
+*/
+
+/*
+** f3: { target { { any-opts "-mcmodel=medany"  } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv" "-march=rv64gc_zve64d" "-march=rv64gc_zve32f" } } }
+**        lla\s+[ta][0-7],a_b
+**        vsetivli\s+zero,16,e32,m(f2|1|4),ta,ma
 **        vle32.v\s+v\d+,0\([ta][0-7]\)
 **        lla\s+[ta][0-7],a_a
 **        vse32\.v\s+v\d+,0\([ta][0-7]\)
 **        ret
 */
 
+/*
+** f3: { target { { any-opts "-mcmodel=medany --param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" } } }
+**        lla\s+[ta][0-7],a_a
+**        lla\s+[ta][0-7],a_b
+**        vl(1|2|4)re32\.v\s+v\d+,0\([ta][0-7]\)
+**        vs(1|2|4)r\.v\s+v\d+,0\([ta][0-7]\)
+**        ret
+*/
+
 extern struct { __INT32_TYPE__ a[16]; } a_a, a_b;
 
 void f3 ()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c
index 83e5a837730..1e11ac0759f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c
@@ -3,4 +3,5 @@ 
 
 #include "cpymem-strategy.h"
 
-/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 } } */
+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */
+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c
index 800549c8556..6bbcb54dec1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c
@@ -3,4 +3,5 @@ 
 
 #include "cpymem-strategy.h"
 
-/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 } } */
+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */
+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */