| Message ID | 20231219014455.33713-1-xuli1@eswincomputing.com |
|---|---|
| State | New |
| Headers | show |
| Series | testsuite: Fix cpymem-2.c dump checks under different riscv-sim for RVV. | expand |
OK。 juzhe.zhong@rivai.ai From: Li Xu Date: 2023-12-19 09:44 To: gcc-patches CC: kito.cheng; palmer; juzhe.zhong; xuli Subject: [PATCH] testsuite: Fix cpymem-2.c dump checks under different riscv-sim for RVV. From: xuli <xuli1@eswincomputing.com> gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/cpymem-2.c: Fix checks. --- .../gcc.target/riscv/rvv/base/cpymem-2.c | 44 ++++++++++++++----- 1 file changed, 33 insertions(+), 11 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c index 7b706b6ef52..f1914a36161 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O1" } */ +/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-add-options riscv_v } */ /* { dg-final { check-function-bodies "**" "" } } */ @@ -8,23 +8,38 @@ typedef struct { char c[32]; } c32; typedef struct { short s; char c[30]; } s16; /* A short struct copy can use vsetivli. -** f1: -** vsetivli\s+zero,16,e8,m1,ta,ma +** f1: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } +** vsetivli\s+zero,16,e8,m(1|f8|f2|f4),ta,ma ** vle8.v\s+v1,0\(a1\) ** vse8.v\s+v1,0\(a0\) ** ret */ + +/* +** f1: { target { { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } +** vl1re8.v\s+v1,0\(a1\) +** vs1r.v\s+v1,0\(a0\) +** ret +*/ + void f1 (c16 *a, c16* b) { *a = *b; } /* A longer one needs li. -** f2: +** f2: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } ** li\s+[ta][0-7],32 -** vsetvli\s+zero,[ta][0-7],e8,m2,ta,ma -** vle8.v\s+v2,0\(a1\) -** vse8.v\s+v2,0\(a0\) +** vsetvli\s+zero,[ta][0-7],e8,m(f4|f2|1|2|8),ta,ma +** vle8.v\s+v(1|2|8),0\(a1\) +** vse8.v\s+v(1|2|8),0\(a0\) +** ret +*/ + +/* +** f2: { target { { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } +** vl2re8.v\s+v2,0\(a1\) +** vs2r.v\s+v2,0\(a0\) ** ret */ void f2 (c32 *a, c32* b) @@ -34,10 +49,17 @@ void f2 (c32 *a, c32* b) /* A 32 byte struct is still short enough for vsetivli if we can use an element width larger than 8. -** f3: -** vsetivli\s+zero,16,e16,m2,ta,ma -** vle16.v\s+v2,0\(a1\) -** vse16.v\s+v2,0\(a0\) +** f3: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } +** vsetivli\s+zero,16,e16,m(f2|f4|1|2|8),ta,ma +** vle16.v\s+v(1|2|8),0\(a1\) +** vse16.v\s+v(1|2|8),0\(a0\) +** ret +*/ + +/* +** f3: { target { { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } +** vl2re16.v\s+v2,0\(a1\) +** vs2r.v\s+v2,0\(a0\) ** ret */ void f3 (s16 *a, s16* b)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c index 7b706b6ef52..f1914a36161 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O1" } */ +/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-add-options riscv_v } */ /* { dg-final { check-function-bodies "**" "" } } */ @@ -8,23 +8,38 @@ typedef struct { char c[32]; } c32; typedef struct { short s; char c[30]; } s16; /* A short struct copy can use vsetivli. -** f1: -** vsetivli\s+zero,16,e8,m1,ta,ma +** f1: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } +** vsetivli\s+zero,16,e8,m(1|f8|f2|f4),ta,ma ** vle8.v\s+v1,0\(a1\) ** vse8.v\s+v1,0\(a0\) ** ret */ + +/* +** f1: { target { { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } +** vl1re8.v\s+v1,0\(a1\) +** vs1r.v\s+v1,0\(a0\) +** ret +*/ + void f1 (c16 *a, c16* b) { *a = *b; } /* A longer one needs li. -** f2: +** f2: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } ** li\s+[ta][0-7],32 -** vsetvli\s+zero,[ta][0-7],e8,m2,ta,ma -** vle8.v\s+v2,0\(a1\) -** vse8.v\s+v2,0\(a0\) +** vsetvli\s+zero,[ta][0-7],e8,m(f4|f2|1|2|8),ta,ma +** vle8.v\s+v(1|2|8),0\(a1\) +** vse8.v\s+v(1|2|8),0\(a0\) +** ret +*/ + +/* +** f2: { target { { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } +** vl2re8.v\s+v2,0\(a1\) +** vs2r.v\s+v2,0\(a0\) ** ret */ void f2 (c32 *a, c32* b) @@ -34,10 +49,17 @@ void f2 (c32 *a, c32* b) /* A 32 byte struct is still short enough for vsetivli if we can use an element width larger than 8. -** f3: -** vsetivli\s+zero,16,e16,m2,ta,ma -** vle16.v\s+v2,0\(a1\) -** vse16.v\s+v2,0\(a0\) +** f3: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } +** vsetivli\s+zero,16,e16,m(f2|f4|1|2|8),ta,ma +** vle16.v\s+v(1|2|8),0\(a1\) +** vse16.v\s+v(1|2|8),0\(a0\) +** ret +*/ + +/* +** f3: { target { { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } +** vl2re16.v\s+v2,0\(a1\) +** vs2r.v\s+v2,0\(a0\) ** ret */ void f3 (s16 *a, s16* b)
From: xuli <xuli1@eswincomputing.com> gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/cpymem-2.c: Fix checks. --- .../gcc.target/riscv/rvv/base/cpymem-2.c | 44 ++++++++++++++----- 1 file changed, 33 insertions(+), 11 deletions(-)