@@ -831,7 +831,7 @@
vfsqrt,vfrecp,vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
vfclass,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
- vimovxv,vfmovfv,vlsegde,vlsegdff")
+ vimovxv,vfmovfv,vlsegde,vlsegdff,vmiota")
(const_int 7)
(eq_attr "type" "vldm,vstm,vmalu,vmalu")
(const_int 5)
new file mode 100644
@@ -0,0 +1,75 @@
+/* { dg-do run } */
+/* { dg-require-effective-target riscv_v } */
+/* { dg-options "--param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */
+
+#define N 128
+
+__attribute__ ((noinline)) int
+main1 (unsigned short a0, unsigned short a1, unsigned short a2,
+ unsigned short a3, unsigned short a4, unsigned short a5,
+ unsigned short a6, unsigned short a7, unsigned short a8,
+ unsigned short a9, unsigned short a10, unsigned short a11,
+ unsigned short a12, unsigned short a13, unsigned short a14,
+ unsigned short a15, unsigned char b0, unsigned char b1)
+{
+ int i;
+ unsigned short out[N*16];
+ unsigned char out2[N*16];
+
+ for (i = 0; i < N; i++)
+ {
+ out[i*16] = a8;
+ out[i*16 + 1] = a7;
+ out[i*16 + 2] = a1;
+ out[i*16 + 3] = a2;
+ out[i*16 + 4] = a8;
+ out[i*16 + 5] = a5;
+ out[i*16 + 6] = a5;
+ out[i*16 + 7] = a4;
+ out[i*16 + 8] = a12;
+ out[i*16 + 9] = a13;
+ out[i*16 + 10] = a14;
+ out[i*16 + 11] = a15;
+ out[i*16 + 12] = a6;
+ out[i*16 + 13] = a9;
+ out[i*16 + 14] = a0;
+ out[i*16 + 15] = a7;
+
+ out2[i*2] = b1;
+ out2[i*2+1] = b0;
+ }
+
+ /* check results: */
+#pragma GCC novector
+ for (i = 0; i < N; i++)
+ {
+ if (out[i*16] != a8
+ || out[i*16 + 1] != a7
+ || out[i*16 + 2] != a1
+ || out[i*16 + 3] != a2
+ || out[i*16 + 4] != a8
+ || out[i*16 + 5] != a5
+ || out[i*16 + 6] != a5
+ || out[i*16 + 7] != a4
+ || out[i*16 + 8] != a12
+ || out[i*16 + 9] != a13
+ || out[i*16 + 10] != a14
+ || out[i*16 + 11] != a15
+ || out[i*16 + 12] != a6
+ || out[i*16 + 13] != a9
+ || out[i*16 + 14] != a0
+ || out[i*16 + 15] != a7
+ || out2[i*2] != b1
+ || out2[i*2 + 1] != b0)
+ __builtin_abort ();
+ }
+
+ return 0;
+}
+
+int main (void)
+{
+ main1 (15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,20,21);
+
+ return 0;
+}
From: Juzhe-Zhong <juzhe.zhong@rivai.ai> This patch fixes the following FAIL when LMUL = 8: riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medany/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=scalable FAIL: gcc.dg/vect/slp-multitypes-2.c execution test The rootcause is we missed viota avl_type, so we end up with incorrect vsetvl configuration: vsetvli zero,a2,e64,m8,ta,ma viota.m v16,v0 'a2' value is a garbage value. After this patch: vsetvli a4,zero,e64,m8,ta,ma viota.m v16,v0 gcc/ChangeLog: * config/riscv/vector.md: Add viota avl_type attribute. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/bug-2.c: New test. --- gcc/config/riscv/vector.md | 2 +- .../gcc.target/riscv/rvv/autovec/bug-2.c | 75 +++++++++++++++++++ 2 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c