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bh=R+mme+BMMS1HP2RdCN5aZbXm0hguzN48BhGQtjpCZGs=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=nnN1WuJzQFko3fi+T42fsNC8xE7jLVphlsMXfLZw9uAqyrdDE/+13912n9ZYF4ilZvOJ77KV+qIM+u2SER5/xldgd+4g+iR6vxBis01SQBoWyBX72ht9bwGvInbWG3w1GG7eepeqOWWiUmISRU3V/NhDzAw1W8ufVV5d9gbR2Ho= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp64t1701951143tyl7xc30 Received: from server1.localdomain ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 07 Dec 2023 20:12:22 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: 90EFqYDyPxDfebpJmLk/BXQEkAKmbcFMlyIBKKojmySFa6SIst7saTrIjFDUc otPDoNLtiGdswa1AHA9ihZ03DQzmRIh86V8qHDxFRWNfEsiWw1BJ+336k5NFhsTcyHgKQdl +adhQxQ0DSTZvBP2OjaW0nsvE1sy2IpvL4Xn/Ljq10R5SFbdJz8KkiMQVJcOr080D5MRwFQ 2wNO7d4kp+XoA/zn9r86rcWGE9WIyAGWQrzU8oZ9LmI221XGSZci3WAkfH4WEltmMus0b/b jZ0sgMMAJ9z3nAQmk4uN6/uwB+G8LRYPgaskGxLNC6NVsu8ndXtRhU5FxzPu6sG/T4cThzx 8Hw9QQ8SoQ8sERCaemdIYLHmNw00j6cJbOB1kXFOAS3sO3jM9MWKqVIMl4cjArsROudwaj7 yBak00nwWuBLyAnZqkFJRA== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 15376226599365006620 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix AVL propagation ICE for vleff/vlsegff Date: Thu, 7 Dec 2023 20:12:20 +0800 Message-Id: <20231207121220.3351398-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch fixes 400 ICEs in full coverage testing: internal compiler error: in validate_change_or_fail, at config/riscv/riscv-v.cc:4597 The root cause is each operand is used in vleff/vlsegff twice: (define_insn "@pred_fault_load" [(set (match_operand:V 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:V (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm, Wc1, Wc1") (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") (match_operand 5 "const_int_operand" " i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:V [(match_operand:V 3 "memory_operand" " m, m, m, m")] UNSPEC_VLEFF) (match_operand:V 2 "vector_merge_operand" " vu, 0, vu, 0"))) (set (reg:SI VL_REGNUM) (unspec:SI [(if_then_else:V (unspec: [(match_dup 1) (match_dup 4) (match_dup 5) (match_dup 6) (match_dup 7) (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:V [(match_dup 3)] UNSPEC_VLEFF) (match_dup 2))] UNSPEC_MODIFY_VL))] Then later instruction change in AVL propagation change ICE: validate_change_or_fail (rinsn, recog_data.operand_loc[index], get_avl_type_rtx (avl_type::NONVLMAX), false); which is the operand change according to location. Such operand change in 2 locations instead of 1. So regenerate pattern for such instructions AVL propagation to fix the ICEs. gcc/ChangeLog: * config/riscv/riscv-avlprop.cc (simplify_replace_avl): New function. (simplify_replace_vlmax_avl): Fix bug. * config/riscv/t-riscv: Add a new include file. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/avl_prop-2.c: New test. --- gcc/config/riscv/riscv-avlprop.cc | 36 +++++++++++++--- gcc/config/riscv/t-riscv | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_prop-2.c | 41 +++++++++++++++++++ 3 files changed, 72 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c diff --git a/gcc/config/riscv/riscv-avlprop.cc b/gcc/config/riscv/riscv-avlprop.cc index d298f0ea456..02f006742f1 100644 --- a/gcc/config/riscv/riscv-avlprop.cc +++ b/gcc/config/riscv/riscv-avlprop.cc @@ -79,6 +79,7 @@ along with GCC; see the file COPYING3. If not see #include "cfgcleanup.h" #include "insn-attr.h" #include "tm-constrs.h" +#include "insn-opinit.h" using namespace rtl_ssa; using namespace riscv_vector; @@ -142,6 +143,34 @@ get_insn_vtype_mode (rtx_insn *rinsn) return GET_MODE (recog_data.operand[mode_idx]); } +/* Return new pattern for AVL propagation. + Normally, we just replace AVL operand only for most + of the instructions. However, for instructions like + fault load which use AVL TYPE twice in the pattern which + will cause ICE in the later AVL TYPE change so we regenerate + the whole pattern for such instructions. */ +static rtx +simplify_replace_avl (rtx_insn *rinsn, rtx new_avl) +{ + /* Replace AVL operand. */ + extract_insn_cached (rinsn); + rtx avl = recog_data.operand[get_attr_vl_op_idx (rinsn)]; + int count = count_regno_occurrences (rinsn, REGNO (avl)); + gcc_assert (count == 1); + rtx new_pat = simplify_replace_rtx (PATTERN (rinsn), avl, new_avl); + if (get_attr_type (rinsn) == TYPE_VLDFF + || get_attr_type (rinsn) == TYPE_VLSEGDFF) + new_pat + = gen_pred_fault_load (recog_data.operand_mode[0], recog_data.operand[0], + recog_data.operand[1], recog_data.operand[2], + recog_data.operand[3], new_avl, + recog_data.operand[5], recog_data.operand[6], + get_avl_type_rtx (avl_type::NONVLMAX)); + else + new_pat = simplify_replace_rtx (PATTERN (rinsn), avl, new_avl); + return new_pat; +} + static void simplify_replace_vlmax_avl (rtx_insn *rinsn, rtx new_avl) { @@ -152,12 +181,7 @@ simplify_replace_vlmax_avl (rtx_insn *rinsn, rtx new_avl) fprintf (dump_file, "into: "); print_rtl_single (dump_file, rinsn); } - /* Replace AVL operand. */ - extract_insn_cached (rinsn); - rtx avl = recog_data.operand[get_attr_vl_op_idx (rinsn)]; - int count = count_regno_occurrences (rinsn, REGNO (avl)); - gcc_assert (count == 1); - rtx new_pat = simplify_replace_rtx (PATTERN (rinsn), avl, new_avl); + rtx new_pat = simplify_replace_avl (rinsn, new_avl); validate_change_or_fail (rinsn, &PATTERN (rinsn), new_pat, false); /* Change AVL TYPE into NONVLMAX if it is VLMAX. */ diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv index 3b9686daa58..372bb77c726 100644 --- a/gcc/config/riscv/t-riscv +++ b/gcc/config/riscv/t-riscv @@ -81,7 +81,7 @@ riscv-vector-costs.o: $(srcdir)/config/riscv/riscv-vector-costs.cc \ riscv-avlprop.o: $(srcdir)/config/riscv/riscv-avlprop.cc \ $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) $(REGS_H) \ $(TARGET_H) tree-pass.h df.h rtl-ssa.h cfgcleanup.h insn-attr.h \ - tm-constrs.h + tm-constrs.h insn-opinit.h $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/riscv/riscv-avlprop.cc diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c new file mode 100644 index 00000000000..fdef8e37ce5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */ + +int d0, sj, v0, rp, zi; + +void +zn(void) +{ + if (v0 != 0) + { + int *js, *r3; + int pm, gc; + + for (gc = 0; gc < 1; ++gc) + { + sj = 1; + while (sj != 0) + ; + } + r3 = ± + *js = (long)&gc; +ka: + for (d0 = 0; d0 < 2; ++d0) + { + d0 = zi; + if (zi) + for (pm = 2; pm != 0; --pm) + ; + } + while (*r3 != 0) + { + while (pm) + ; + ++r3; + } + } + rp = 0; + goto ka; +} + +/* { dg-final { scan-assembler-times {vsetivli\tzero,\s*1} 2 } } */