[v2,3/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1)

Message ID	20231118042944.3704-1-cooper.joshua@linux.alibaba.com
State	New
Headers	show Return-Path: <gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 65D1B3858D1E From: "Jun Sha (Joshua)" <cooper.joshua@linux.alibaba.com> To: gcc-patches@gcc.gnu.org Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu, "Jun Sha (Joshua)" <cooper.joshua@linux.alibaba.com> Subject: [PATCH v2 3/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1) Date: Sat, 18 Nov 2023 12:29:44 +0800 Message-Id: <20231118042944.3704-1-cooper.joshua@linux.alibaba.com> In-Reply-To: <20231118042258.3545-1-cooper.joshua@linux.alibaba.com> References: <20231118042258.3545-1-cooper.joshua@linux.alibaba.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org
Series	RISC-V: Support XTheadVector extensions \| expand [v2,0/9] RISC-V: Support XTheadVector extensions [v2,1/9] RISC-V: minimal support for xtheadvector [v2,2/9] RISC-V: Handle differences between xtheadvector and vector [v2,3/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1) [v2,4/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part2) [v2,5/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part3) [v2,6/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part4) [v2,8/9] RISC-V: Add support for xtheadvector-specific load/store intrinsics [v2,9/9] RISC-V: Disable fractional type intrinsics for the XTheadVector extension

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-1.c new file mode 100644 index 00000000000..172dfb6c228 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-1.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** th.vse\.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f1 (void * in, void *out) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vadd_vv_i32m1 (v2, v2, 4); + vint32m1_t v4 = __riscv_vadd_vv_i32m1_tu (v3, v2, v2, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** th.vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f2 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vadd_vv_i32m1 (v2, v2, 4); + vint32m1_t v4 = __riscv_vadd_vv_i32m1_m (mask, v3, v3, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** th.vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f3 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vadd_vv_i32m1 (v2, v2, 4); + vint32m1_t v4 = __riscv_vadd_vv_i32m1_tumu (mask, v3, v2, v2, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-3.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-3.c new file mode 100644 index 00000000000..c89635ab85b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-3.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +#include "riscv_th_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmseq_vv_i32m1_b32_m (m3, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmslt_vv_i32m1_b32_m (m3, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-not {th.vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-4.c new file mode 100644 index 00000000000..3cca8a47ef1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-4.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +#include "riscv_th_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmseq_vv_i32m1_b32_mu (m3, m3, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmslt_vv_i32m1_b32_mu (m3, m3, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-not {th.vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-5.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-5.c new file mode 100644 index 00000000000..45a679b424c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-5.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +#include "riscv_th_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmseq_vv_i32m1_b32_mu (mask, m3, v, v, 4); + m4 = __riscv_vmseq_vv_i32m1_b32_m (m4, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmslt_vv_i32m1_b32_mu (mask, m3, v, v, 4); + m4 = __riscv_vmslt_vv_i32m1_b32_m (m4, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-times {th.vmv} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-6.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-6.c new file mode 100644 index 00000000000..1ef85d556d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-6.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +#include "riscv_th_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = __riscv_vlm_v_b32 (in, 4); + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vv_i32m1_b32 (v, v2, 4); + vbool32_t m4 = __riscv_vmseq_vv_i32m1_b32_mu (m3, mask, v, v, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = __riscv_vlm_v_b32 (in, 4); + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vv_i32m1_b32 (v, v2, 4); + vbool32_t m4 = __riscv_vmslt_vv_i32m1_b32_mu (m3, mask, v, v, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-times {th.vmv} 2 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-7.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-7.c new file mode 100644 index 00000000000..bbef0d43664 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-7.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +#include "riscv_th_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmseq_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmseq_vv_i32m1_b32_m (m3, v2, v2, 4); + m4 = __riscv_vmseq_vv_i32m1_b32_m (m4, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vbool32_t m3 = __riscv_vmslt_vv_i32m1_b32 (v, v, 4); + vbool32_t m4 = __riscv_vmslt_vv_i32m1_b32_m (m3, v2, v2, 4); + m4 = __riscv_vmslt_vv_i32m1_b32_m (m4, v2, v2, 4); + __riscv_vsm_v_b32 (out, m4, 4); +} + +/* { dg-final { scan-assembler-not {th.vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-1.c new file mode 100644 index 00000000000..ed9b0c7c01f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-1.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_m (mask, v3, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-10.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-10.c new file mode 100644 index 00000000000..89616f3d3b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-10.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vse\.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vand_vx_i32m1_tu (v3, v2, -16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vand\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vand_vx_i32m1_m (mask, v3, -16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vand\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vand_vx_i32m1_tumu (mask, v3, v2, -16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-2.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-2.c new file mode 100644 index 00000000000..e64543b1aac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-2.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vse\.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tu (v3, v2, -16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_m (mask, v3, -16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tumu (mask, v3, v2, -16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-3.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-3.c new file mode 100644 index 00000000000..4775a4af325 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-3.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vse\.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, 15, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tu (v3, v2, 15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, 15, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_m (mask, v3, 15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, 15, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tumu (mask, v3, v2, 15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-4.c new file mode 100644 index 00000000000..6dd00c8b3b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-4.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tu (v3, v2, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** ... +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_m (mask, v3, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** ... +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tumu (mask, v3, v2, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-5.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-5.c new file mode 100644 index 00000000000..86606537b14 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-5.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vxor_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vxor_vx_i32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vxor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vxor_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vxor_vx_i32m1_m (mask, v3, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vxor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vxor_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vxor_vx_i32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-6.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-6.c new file mode 100644 index 00000000000..e7bede15b86 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-6.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vse\.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vxor_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vxor_vx_i32m1_tu (v3, v2, -16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vxor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vxor_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vxor_vx_i32m1_m (mask, v3, -16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vxor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vxor_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vxor_vx_i32m1_tumu (mask, v3, v2, -16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-7.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-7.c new file mode 100644 index 00000000000..1cd688919f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-7.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vse\.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vxor_vx_i32m1 (v2, 15, 4); + vint32m1_t v4 = __riscv_vxor_vx_i32m1_tu (v3, v2, 15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vxor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vxor_vx_i32m1 (v2, 15, 4); + vint32m1_t v4 = __riscv_vxor_vx_i32m1_m (mask, v3, 15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vxor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vxor_vx_i32m1 (v2, 15, 4); + vint32m1_t v4 = __riscv_vxor_vx_i32m1_tumu (mask, v3, v2, 15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-8.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-8.c new file mode 100644 index 00000000000..70f525d30ed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-8.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vxor_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vxor_vx_i32m1_tu (v3, v2, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** ... +** th.vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vxor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vxor_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vxor_vx_i32m1_m (mask, v3, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** ... +** th.vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vxor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vxor_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vxor_vx_i32m1_tumu (mask, v3, v2, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-9.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-9.c new file mode 100644 index 00000000000..0b248b68e0c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-9.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vand_vx_i32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vand\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vand_vx_i32m1_m (mask, v3, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0$[a-x0-9]+$ +** ... +** th.vle\.v\tv[0-9]+,0$[a-x0-9]+$ +** th.vle.v\tv[0-9]+,0$[a-x0-9]+$,v0.t +** th.vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vand\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0$[a-x0-9]+$ +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vand_vx_i32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/rvv-xtheadvector.exp b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/rvv-xtheadvector.exp new file mode 100644 index 00000000000..ffc8fee575f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/rvv-xtheadvector.exp @@ -0,0 +1,41 @@ +# Copyright (C) 2017-2020 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't a RISC-V target. +if ![istarget riscv*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ + "-I$srcdir/$subdir/../ -std=gnu99 -O2" $DEFAULT_CFLAGS + +# All done. +dg-finish \ No newline at end of file

[v2,3/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1)

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