diff mbox series

Avoid generating RTL code when d->testing_p.

Message ID 20231106103103.3374589-1-hongtao.liu@intel.com
State New
Headers show
Series Avoid generating RTL code when d->testing_p. | expand

Commit Message

Liu, Hongtao Nov. 6, 2023, 10:31 a.m. UTC 
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ready push to trunk.

gcc/ChangeLog:

	PR target/112393
	* config/i386/i386-expand.cc (ix86_expand_vec_perm_vpermt2):
	Avoid generating RTL code when d->testing_p.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr112393.c: New test.
---
 gcc/config/i386/i386-expand.cc           |  3 +++
 gcc/testsuite/gcc.target/i386/pr112393.c | 20 ++++++++++++++++++++
 2 files changed, 23 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr112393.c
diff mbox series

Patch

diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 6ae5830037d..8fad73c1549 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -5245,6 +5245,9 @@  ix86_expand_vec_perm_vpermt2 (rtx target, rtx mask, rtx op0, rtx op1,
   if (gen == NULL)
     return false;
 
+  if (d && d->testing_p)
+    return true;
+
   /* ix86_expand_vec_perm_vpermt2 is called from both const and non-const
      expander, so args are either in d, or in op0, op1 etc.  */
   if (d)
diff --git a/gcc/testsuite/gcc.target/i386/pr112393.c b/gcc/testsuite/gcc.target/i386/pr112393.c
new file mode 100644
index 00000000000..c5c5b95b188
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr112393.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -Wuninitialized" } */
+typedef _Float16 __attribute__((__vector_size__ (32))) V;
+
+V v;
+
+void
+foo (void)
+{
+  (void) __builtin_shufflevector (v, __builtin_shufflevector (v, (V){},
+                                                              3, 0, 2, 2,
+							      5, 6, 3, 7, 5,
+							      6, 0, 8, 6, 4,
+							      3, 2, 8, 9, 5,
+							      8, 8, 7, 5, 4,
+							      8, 9, 1, 2, 4,
+							      9, 9, 7),
+                                  40, 33);
+}
+