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Mon, 30 Oct 2023 17:52:08 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: Patrick O'Neill Subject: [PATCH 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores Date: Mon, 30 Oct 2023 17:49:28 -0700 Message-ID: <20231031004929.1435217-1-patrick@rivosinc.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Non-atomic targets are currently prevented from using the optimized fencing for seq_cst load/seq_cst store. This patch removes that constraint. gcc/ChangeLog: * config/riscv/sync-rvwmo.md (atomic_load_rvwmo): Remove TARGET_ATOMIC constraint (atomic_store_rvwmo): Ditto. * config/riscv/sync-ztso.md (atomic_load_ztso): Ditto. (atomic_store_ztso): Ditto. * config/riscv/sync.md (atomic_load): Ditto. (atomic_store): Ditto. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/sync-rvwmo.md | 4 ++-- gcc/config/riscv/sync-ztso.md | 4 ++-- gcc/config/riscv/sync.md | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) -- 2.34.1 diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md index cb641ea9ec3..c35eae15334 100644 --- a/gcc/config/riscv/sync-rvwmo.md +++ b/gcc/config/riscv/sync-rvwmo.md @@ -52,7 +52,7 @@ [(match_operand:GPR 1 "memory_operand" "A") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_LOAD))] - "TARGET_ATOMIC && !TARGET_ZTSO" + "!TARGET_ZTSO" { enum memmodel model = (enum memmodel) INTVAL (operands[2]); model = memmodel_base (model); @@ -78,7 +78,7 @@ [(match_operand:GPR 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] - "TARGET_ATOMIC && !TARGET_ZTSO" + "!TARGET_ZTSO" { enum memmodel model = (enum memmodel) INTVAL (operands[2]); model = memmodel_base (model); diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md index 7bb15b7ab8c..6fdfa912a2c 100644 --- a/gcc/config/riscv/sync-ztso.md +++ b/gcc/config/riscv/sync-ztso.md @@ -46,7 +46,7 @@ [(match_operand:GPR 1 "memory_operand" "A") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_LOAD))] - "TARGET_ATOMIC && TARGET_ZTSO" + "TARGET_ZTSO" { enum memmodel model = (enum memmodel) INTVAL (operands[2]); model = memmodel_base (model); @@ -66,7 +66,7 @@ [(match_operand:GPR 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] - "TARGET_ATOMIC && TARGET_ZTSO" + "TARGET_ZTSO" { enum memmodel model = (enum memmodel) INTVAL (operands[2]); model = memmodel_base (model); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 6ff3493b5ce..ec9d4b4f59e 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -60,7 +60,7 @@ [(match_operand:GPR 0 "register_operand") (match_operand:GPR 1 "memory_operand") (match_operand:SI 2 "const_int_operand")] ;; model - "TARGET_ATOMIC" + "" { if (TARGET_ZTSO) emit_insn (gen_atomic_load_ztso (operands[0], operands[1], @@ -75,7 +75,7 @@ [(match_operand:GPR 0 "memory_operand") (match_operand:GPR 1 "reg_or_0_operand") (match_operand:SI 2 "const_int_operand")] ;; model - "TARGET_ATOMIC" + "" { if (TARGET_ZTSO) emit_insn (gen_atomic_store_ztso (operands[0], operands[1],