From patchwork Thu Oct 12 06:02:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 1847232 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=kGEdPmQ0; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S5fH31HB6z1yqj for ; Thu, 12 Oct 2023 17:04:29 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BF2DC385802F for ; Thu, 12 Oct 2023 06:04:27 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 902913858CDA for ; Thu, 12 Oct 2023 06:04:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 902913858CDA Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697090654; x=1728626654; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kPPh4CSZuENVmtHwj/skIUbKsmIxAYjrXEz1bo+SGB0=; b=kGEdPmQ0HlsyQLyLV7QWczeCEMRvr1lf4H9efKXCusi/kHUPev7KcX9I lNEOfLIxVP7BZEY7N6oGgUw6J/9TnuPLN0bfRPylMjveDb+vi0lYHbckx c6TXKrADJTF7nfyj3W2tIFwVtMSPwKa73cZYPETnxj4V7WcN7hpIouepg mDHp2Yhz5hNRPfdWcCOPDS8KPdKGgwhDs7RUmDVwXKFTTUmkP+OrLKLta A09VQ6Q4VT8Rn1fuvMw21dGiOF4NYL3DY26HOxzjMdpaDMxGA4OXQERGq FqyfPrcFyde74T0lbRMpALMm1XL4hPkXHmsCBJOIRnm+ckSIObgxDV0PB A==; X-IronPort-AV: E=McAfee;i="6600,9927,10860"; a="471096523" X-IronPort-AV: E=Sophos;i="6.03,218,1694761200"; d="scan'208";a="471096523" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2023 23:04:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10860"; a="877984838" X-IronPort-AV: E=Sophos;i="6.03,218,1694761200"; d="scan'208";a="877984838" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga004.jf.intel.com with ESMTP; 11 Oct 2023 23:04:10 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 8C95210056F6; Thu, 12 Oct 2023 14:04:09 +0800 (CST) From: liuhongt To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com Subject: [PATCH 2/2] Support 32/64-bit vectorization for conversion between _Float16 and integer/float. Date: Thu, 12 Oct 2023 14:02:09 +0800 Message-Id: <20231012060209.4130200-2-hongtao.liu@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231012060209.4130200-1-hongtao.liu@intel.com> References: <20231012060209.4130200-1-hongtao.liu@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ready push to trunk. gcc/ChangeLog: * config/i386/mmx.md (V2FI_32): New mode iterator (movd_v2hf_to_sse): Rename to .. (movd__to_sse): .. this. (movd_v2hf_to_sse_reg): Rename to .. (movd__to_sse_reg): .. this. (fix_trunc2): New expander. (fix_truncv2hfv2si2): Ditto. (float2): Ditto. (floatv2siv2hf2): Ditto. (extendv2hfv2sf2): Ditto. (truncv2sfv2hf2): Ditto. * config/i386/sse.md (*vec_concatv8hf_movss): Rename to .. (*vec_concat_movss): .. this. gcc/testsuite/ChangeLog: * gcc.target/i386/part-vect-hf-convert-1.c: New test. --- gcc/config/i386/mmx.md | 164 ++++++++++++++++-- gcc/config/i386/sse.md | 12 +- .../gcc.target/i386/part-vect-hf-convert-1.c | 111 ++++++++++++ 3 files changed, 262 insertions(+), 25 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/part-vect-hf-convert-1.c diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 8375100d4bf..be2a9026c44 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -60,6 +60,7 @@ (define_mode_iterator MMXMODE248 [V4HI V2SI V1DI]) ;; All 4-byte integer/float16 vector modes (define_mode_iterator V_32 [V4QI V2HI V1SI V2HF V2BF]) +(define_mode_iterator V2FI_32 [V2HF V2BF V2HI]) ;; 4-byte integer vector modes (define_mode_iterator VI_32 [V4QI V2HI]) @@ -79,7 +80,7 @@ (define_mode_iterator V_16_32_64 ;; V2S* modes (define_mode_iterator V2FI [V2SF V2SI]) -(define_mode_iterator V2FI_V4HF [V2SF V2SI V4HF]) +(define_mode_iterator V24FI [V2SF V2SI V4HF V4HI]) ;; Mapping from integer vector mode to mnemonic suffix (define_mode_attr mmxvecsize [(V8QI "b") (V4QI "b") (V2QI "b") @@ -100,7 +101,7 @@ (define_mode_attr mmxdoublemode ;; Mapping of vector float modes to an integer mode of the same size (define_mode_attr mmxintvecmode [(V2SF "V2SI") (V2SI "V2SI") (V4HI "V4HI") (V8QI "V8QI") - (V4HF "V4HF") (V2HF "V2HI")]) + (V4HF "V4HI") (V2HF "V2HI")]) (define_mode_attr mmxintvecmodelower [(V2SF "v2si") (V2SI "v2si") (V4HI "v4hi") (V8QI "v8qi") @@ -108,7 +109,7 @@ (define_mode_attr mmxintvecmodelower ;; Mapping of vector modes to a vector mode of double size (define_mode_attr mmxdoublevecmode - [(V2SF "V4SF") (V2SI "V4SI") (V4HF "V8HF")]) + [(V2SF "V4SF") (V2SI "V4SI") (V4HF "V8HF") (V4HI "V8HI")]) ;; Mapping of vector modes back to the scalar modes (define_mode_attr mmxscalarmode @@ -600,7 +601,7 @@ (define_insn "sse_movntq" (define_expand "movq__to_sse" [(set (match_operand: 0 "register_operand") (vec_concat: - (match_operand:V2FI_V4HF 1 "nonimmediate_operand") + (match_operand:V24FI 1 "nonimmediate_operand") (match_dup 2)))] "TARGET_SSE2" { @@ -1967,31 +1968,40 @@ (define_expand "divv4hf3" DONE; }) -(define_mode_attr mov_to_sse_suffix [(V2HF "d") (V4HF "q")]) -(define_expand "movd_v2hf_to_sse" - [(set (match_operand:V8HF 0 "register_operand") - (vec_merge:V8HF - (vec_duplicate:V8HF - (match_operand:V2HF 1 "nonimmediate_operand")) +(define_mode_attr mov_to_sse_suffix + [(V2HF "d") (V4HF "q") (V2HI "d") (V4HI "q")]) + +(define_mode_attr mmxxmmmode + [(V2HF "V8HF") (V2HI "V8HI") (V2BF "V8BF")]) + +(define_mode_attr mmxxmmmodelower + [(V2HF "v8hf") (V2HI "v8hi") (V2BF "v8bf")]) + +(define_expand "movd__to_sse" + [(set (match_operand: 0 "register_operand") + (vec_merge: + (vec_duplicate: + (match_operand:V2FI_32 1 "nonimmediate_operand")) (match_dup 2) (const_int 3)))] "TARGET_SSE" { if (!flag_trapping_math) { - rtx op1 = force_reg (V2HFmode, operands[1]); - emit_move_insn (operands[0], lowpart_subreg (V8HFmode, op1, V2HFmode)); + rtx op1 = force_reg (mode, operands[1]); + emit_move_insn (operands[0], + lowpart_subreg (mode, op1, mode)); DONE; } - operands[2] = CONST0_RTX (V8HFmode); + operands[2] = CONST0_RTX (mode); }) -(define_expand "movd_v2hf_to_sse_reg" - [(set (match_operand:V8HF 0 "register_operand") - (vec_merge:V8HF - (vec_duplicate:V8HF - (match_operand:V2HF 1 "nonimmediate_operand")) - (match_operand:V8HF 2 "register_operand") +(define_expand "movd__to_sse_reg" + [(set (match_operand: 0 "register_operand") + (vec_merge: + (vec_duplicate: + (match_operand:V2FI_32 1 "nonimmediate_operand")) + (match_operand: 2 "register_operand") (const_int 3)))] "TARGET_SSE") @@ -2353,6 +2363,122 @@ (define_expand "signbit2" "TARGET_SSE2" "operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (mode)-1);") +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Parallel single-precision floating point conversion operations +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define_expand "fix_trunc2" + [(set (match_operand: 0 "register_operand") + (any_fix: + (match_operand:VHF_32_64 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math" +{ + rtx op1 = gen_reg_rtx (V8HFmode); + rtx op0 = gen_reg_rtx (V8HImode); + + emit_insn (gen_mov__to_sse (op1, operands[1])); + + emit_insn (gen_fix_truncv8hfv8hi2 (op0, op1)); + + emit_move_insn (operands[0], + lowpart_subreg (mode, op0, V8HImode)); + DONE; +}) + +(define_expand "fix_truncv2hfv2si2" + [(set (match_operand:V2SI 0 "register_operand") + (any_fix:V2SI + (match_operand:V2HF 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL + && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math" +{ + rtx op1 = gen_reg_rtx (V8HFmode); + rtx op0 = gen_reg_rtx (V4SImode); + + emit_insn (gen_movd_v2hf_to_sse (op1, operands[1])); + + emit_insn (gen_avx512fp16_fix_truncv4si2 (op0, op1)); + + emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode)); + DONE; +}) + +(define_expand "float2" + [(set (match_operand:VHF_32_64 0 "register_operand") + (any_float:VHF_32_64 + (match_operand: 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math" +{ + rtx op1 = gen_reg_rtx (V8HImode); + rtx op0 = gen_reg_rtx (V8HFmode); + + rtx (*gen_movd_sse) (rtx, rtx) + = gen_mov__to_sse; + emit_insn (gen_movd_sse (op1, operands[1])); + + emit_insn (gen_floatv8hiv8hf2 (op0, op1)); + + emit_move_insn (operands[0], + lowpart_subreg (mode, op0, V8HFmode)); + DONE; +}) + +(define_expand "floatv2siv2hf2" + [(set (match_operand:V2HF 0 "register_operand") + (any_float:V2HF + (match_operand:V2SI 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL + && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math" +{ + rtx op1 = gen_reg_rtx (V4SImode); + rtx op0 = gen_reg_rtx (V8HFmode); + + emit_insn (gen_movq_v2si_to_sse (op1, operands[1])); + + emit_insn (gen_avx512fp16_floatv4siv4hf2 (op0, op1)); + + emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode)); + DONE; +}) + +(define_expand "extendv2hfv2sf2" + [(set (match_operand:V2SF 0 "register_operand") + (float_extend:V2SF + (match_operand:V2HF 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL + && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math" +{ + rtx op1 = gen_reg_rtx (V8HFmode); + rtx op0 = gen_reg_rtx (V4SFmode); + + emit_insn (gen_movd_v2hf_to_sse (op1, operands[1])); + + emit_insn (gen_avx512fp16_float_extend_phv4sf2 (op0, op1)); + + emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode)); + DONE; +}) + +(define_expand "truncv2sfv2hf2" + [(set (match_operand:V2HF 0 "register_operand") + (float_truncate:V2HF + (match_operand:V2SF 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL + && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math" +{ + rtx op1 = gen_reg_rtx (V4SFmode); + rtx op0 = gen_reg_rtx (V8HFmode); + + emit_insn (gen_movq_v2sf_to_sse (op1, operands[1])); + + emit_insn (gen_avx512fp16_truncv4sfv4hf2 (op0, op1)); + + emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode)); + DONE; +}) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral arithmetic diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 4602edf2374..e9f947291c1 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -10975,12 +10975,12 @@ (define_insn "*vec_concat_0" (set_attr "prefix" "maybe_vex") (set_attr "mode" "DF")]) -(define_insn "*vec_concatv8hf_movss" - [(set (match_operand:V8HF 0 "register_operand" "=x,v,v") - (vec_merge:V8HF - (vec_duplicate:V8HF - (match_operand:V2HF 2 "nonimmediate_operand" "x,m,v")) - (match_operand:V8HF 1 "reg_or_0_operand" "0,C,v" ) +(define_insn "*vec_concat_movss" + [(set (match_operand: 0 "register_operand" "=x,v,v") + (vec_merge: + (vec_duplicate: + (match_operand:V2FI_32 2 "nonimmediate_operand" "x,m,v")) + (match_operand: 1 "reg_or_0_operand" "0,C,v" ) (const_int 3)))] "TARGET_SSE" "@ diff --git a/gcc/testsuite/gcc.target/i386/part-vect-hf-convert-1.c b/gcc/testsuite/gcc.target/i386/part-vect-hf-convert-1.c new file mode 100644 index 00000000000..95426015b58 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/part-vect-hf-convert-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times {(?n)vcvttph2w[ \t]} 2 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvttph2uw[ \t]} 2 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvttph2dq[ \t]} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvttph2udq[ \t]} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvtw2ph[ \t]} 2 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvtuw2ph[ \t]} 2 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvtdq2phx[ \t]} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvtudq2phx[ \t]} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvtph2psx[ \t]} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)vcvtps2phxx[ \t]} 1 } } */ + + +void +fix_32 (short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pa[i] = pb[i]; +} + +void +fix_64 (short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 4; i++) + pa[i] = pb[i]; +} + +void +fixuns_32 (unsigned short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pa[i] = pb[i]; +} + +void +fixuns_64 (unsigned short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 4; i++) + pa[i] = pb[i]; +} + +void +float_32 (short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pb[i] = pa[i]; +} + +void +float_64 (short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 4; i++) + pb[i] = pa[i]; +} + +void +floatuns_32 (unsigned short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pb[i] = pa[i]; +} + +void +floatuns_64 (unsigned short* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 4; i++) + pb[i] = pa[i]; +} + +void +fix_32si (int* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pa[i] = pb[i]; +} + +void +fix_32usi (unsigned int* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pa[i] = pb[i]; +} + +void +float_32si (int* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pb[i] = pa[i]; +} + +void +float_32usi (unsigned int* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pb[i] = pa[i]; +} + +void +float_extend (float* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pa[i] = pb[i]; +} + +void +float_truncate (float* __restrict pa, _Float16* pb) +{ + for (int i = 0; i != 2; i++) + pb[i] = pa[i]; +}