diff mbox series

RISC-V: Enable full coverage vect tests

Message ID 20231011051502.1695577-1-juzhe.zhong@rivai.ai
State New
Headers show
Series RISC-V: Enable full coverage vect tests | expand

Commit Message

钟居哲 Oct. 11, 2023, 5:15 a.m. UTC 
I have analyzed all existing FAILs.

Except these following FAILs need to be addressed:
FAIL: gcc.dg/vect/slp-reduc-7.c -flto -ffat-lto-objects execution test
FAIL: gcc.dg/vect/slp-reduc-7.c execution test
FAIL: gcc.dg/vect/vect-cond-arith-2.c -flto -ffat-lto-objects  scan-tree-dump optimized " = \\.COND_(LEN_)?SUB"
FAIL: gcc.dg/vect/vect-cond-arith-2.c scan-tree-dump optimized " = \\.COND_(LEN_)?SUB"

All other FAILs are dumple fail can be ignored (Confirm ARM SVE also has such FAILs and didn't fix them on either tests or implementation).

Now, It's time to enable full coverage vect tests including vec_unpack, vec_pack, vec_interleave, ... etc.

To see what we are still missing:

Before this patch:

                === gcc Summary ===

# of expected passes            182839
# of unexpected failures        79
# of unexpected successes       11
# of expected failures          1275
# of unresolved testcases       4
# of unsupported tests          4223


After this patch:

                === gcc Summary ===

# of expected passes            183411
# of unexpected failures        93
# of unexpected successes       7
# of expected failures          1285
# of unresolved testcases       4
# of unsupported tests          4157

There is an important issue increased that I have noticed after this patch:

FAIL: gcc.dg/vect/vect-gather-1.c -flto -ffat-lto-objects  scan-tree-dump vect "Loop contains only SLP stmts"
FAIL: gcc.dg/vect/vect-gather-1.c scan-tree-dump vect "Loop contains only SLP stmts"
FAIL: gcc.dg/vect/vect-gather-3.c -flto -ffat-lto-objects  scan-tree-dump vect "Loop contains only SLP stmts"
FAIL: gcc.dg/vect/vect-gather-3.c scan-tree-dump vect "Loop contains only SLP stmts"

It has a related PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111721

I am gonna fix this first in the middle-end after commit this patch.

Ok for trunk ?

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp: Add RVV.

---
 gcc/testsuite/lib/target-supports.exp | 45 ++++++++++++++++++++-------
 1 file changed, 33 insertions(+), 12 deletions(-)

Comments

Robin Dapp Oct. 11, 2023, 6:54 a.m. UTC | #1 
Hi Juzhe,

seems OK to me.  We don't support most of the patterns directly
but as we can and want to vectorize them it makes sens to enable
the tests.

Regards
 Robin
钟居哲 Oct. 11, 2023, 7:04 a.m. UTC | #2 
Thanks. Committed.



juzhe.zhong@rivai.ai
 
From: Robin Dapp
Date: 2023-10-11 14:54
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Enable full coverage vect tests
Hi Juzhe,
 
seems OK to me.  We don't support most of the patterns directly
but as we can and want to vectorize them it makes sens to enable
the tests.
 
Regards
Robin
diff mbox series

Patch

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index b454b07359a..8037dbcee53 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7876,7 +7876,9 @@  proc check_effective_target_vect_sdot_qi { } {
 	     || [istarget aarch64*-*-*]
 	     || [istarget arm*-*-*]
 	     || ([istarget mips*-*-*]
-		 && [et-is-effective-target mips_msa]) }}]
+		 && [et-is-effective-target mips_msa])
+	     || ([istarget riscv*-*-*]
+		 && [check_effective_target_riscv_v]) }}]
 }
 
 # Return 1 if the target plus current options supports a vector
@@ -7891,7 +7893,9 @@  proc check_effective_target_vect_udot_qi { } {
 	     || [istarget arm*-*-*]
 	     || [istarget ia64-*-*]
 	     || ([istarget mips*-*-*]
-		 && [et-is-effective-target mips_msa]) }}]
+		 && [et-is-effective-target mips_msa])
+	     || ([istarget riscv*-*-*]
+		 && [check_effective_target_riscv_v]) }}]
 }
 
 # Return 1 if the target plus current options supports a vector
@@ -7918,7 +7922,9 @@  proc check_effective_target_vect_sdot_hi { } {
 	     || [istarget ia64-*-*]
 	     || [istarget i?86-*-*] || [istarget x86_64-*-*]
 	     || ([istarget mips*-*-*]
-		 && [et-is-effective-target mips_msa]) }}]
+		 && [et-is-effective-target mips_msa])
+	     || ([istarget riscv*-*-*]
+		 && [check_effective_target_riscv_v]) }}]
 }
 
 # Return 1 if the target plus current options supports a vector
@@ -7930,7 +7936,9 @@  proc check_effective_target_vect_udot_hi { } {
     return [check_cached_effective_target_indexed vect_udot_hi {
       expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
 	     || ([istarget mips*-*-*]
-		 && [et-is-effective-target mips_msa]) }}]
+		 && [et-is-effective-target mips_msa])
+	     || ([istarget riscv*-*-*]
+		 && [check_effective_target_riscv_v]) }}]
 }
 
 # Return 1 if the target plus current options supports a vector
@@ -7945,7 +7953,9 @@  proc check_effective_target_vect_usad_char { } {
 	      || ([istarget aarch64*-*-*]
 		  && ![check_effective_target_aarch64_sve])
 	      || ([istarget powerpc*-*-*]
-		  && [check_p9vector_hw_available])}}]
+		  && [check_p9vector_hw_available])
+	      || ([istarget riscv*-*-*]
+		  && [check_effective_target_riscv_v]) }}]
 }
 
 # Return 1 if the target plus current options supports both signed
@@ -7971,8 +7981,10 @@  proc check_effective_target_vect_mulhrs_hi {} {
 # by power-of-2 operations on vectors of 4-byte integers.
 
 proc check_effective_target_vect_sdiv_pow2_si {} {
-    return [expr { [istarget aarch64*-*-*]
-		   && [check_effective_target_aarch64_sve] }]
+    return [expr { ([istarget aarch64*-*-*]
+		    && [check_effective_target_aarch64_sve])
+		   || ([istarget riscv*-*-*]
+		       && [check_effective_target_riscv_v]) }]
 }
 
 # Return 1 if the target plus current options supports a vector
@@ -7992,7 +8004,9 @@  proc check_effective_target_vect_pack_trunc { } {
 		 && [et-is-effective-target mips_msa])
 	     || ([istarget s390*-*-*]
 		 && [check_effective_target_s390_vx])
-             || [istarget amdgcn*-*-*] }}]
+             || [istarget amdgcn*-*-*]
+	     || ([istarget riscv*-*-*]
+		 && [check_effective_target_riscv_v]) }}]
 }
 
 # Return 1 if the target plus current options supports a vector
@@ -8012,7 +8026,9 @@  proc check_effective_target_vect_unpack { } {
 		 && [check_effective_target_arm_little_endian])
 	     || ([istarget s390*-*-*]
 		 && [check_effective_target_s390_vx])
-	     || [istarget amdgcn*-*-*] }}]
+	     || [istarget amdgcn*-*-*]
+	     || ([istarget riscv*-*-*]
+		 && [check_effective_target_riscv_v]) }}]
 }
 
 # Return 1 if the target plus current options does not guarantee
@@ -8662,7 +8678,8 @@  proc check_effective_target_vect_masked_store { } {
 # Return 1 if the target supports vector gather loads via internal functions.
 
 proc check_effective_target_vect_gather_load_ifn { } {
-    return [expr { [check_effective_target_aarch64_sve] }]
+    return [expr { [check_effective_target_aarch64_sve]
+		   || [check_effective_target_riscv_v] }]
 }
 
 # Return 1 if the target supports vector scatter stores.
@@ -8816,7 +8833,9 @@  proc check_effective_target_vect_extract_even_odd { } {
 		 && ([et-is-effective-target mips_msa]
 		     || [et-is-effective-target mpaired_single]))
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx]) }}]
+		 && [check_effective_target_s390_vx])
+             || ([istarget riscv*-*-*]
+		 && [check_effective_target_riscv_v]) }}]
 }
 
 # Return 1 if the target supports vector interleaving, 0 otherwise.
@@ -8832,7 +8851,9 @@  proc check_effective_target_vect_interleave { } {
 		 && ([et-is-effective-target mpaired_single]
 		     || [et-is-effective-target mips_msa]))
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx]) }}]
+		 && [check_effective_target_s390_vx])
+	     || ([istarget riscv*-*-*]
+		 && [check_effective_target_riscv_v]) }}]
 }
 
 foreach N {2 3 4 5 6 7 8} {