diff mbox series

[i386] APX EGPR: fix missing pattern that prohibits egpr

Message ID 20231009022928.1499099-1-hongyu.wang@intel.com
State New
Headers show
Series [i386] APX EGPR: fix missing pattern that prohibits egpr | expand

Commit Message

Hongyu Wang Oct. 9, 2023, 2:29 a.m. UTC 
Thanks, also there is another pattern missed that should use "ja" instead
of Bm. Will commit below changes.

gcc/ChangeLog:

	* config/i386/sse.md (vec_concatv2di): Replace constraint "m"
	with "jm" for alternative 0 and 1 of operand 2.
	(sse4_1_<code><mode>3<mask_name>): Replace constraint "Bm" with
	"ja" for alternative 0 and 1 of operand2.
---
 gcc/config/i386/sse.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 6bffd749c6d..22e43eb3f92 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -16842,7 +16842,7 @@  (define_insn "*sse4_1_<code><mode>3<mask_name>"
   [(set (match_operand:VI24_128 0 "register_operand" "=Yr,*x,<v_Yw>")
 	(umaxmin:VI24_128
 	  (match_operand:VI24_128 1 "vector_operand" "%0,0,<v_Yw>")
-	  (match_operand:VI24_128 2 "vector_operand" "YrBm,*xBm,<v_Yw>m")))]
+	  (match_operand:VI24_128 2 "vector_operand" "Yrja,*xja,<v_Yw>m")))]
   "TARGET_SSE4_1
    && <mask_mode512bit_condition>
    && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
@@ -20638,7 +20638,7 @@  (define_insn "vec_concatv2di"
 	  (match_operand:DI 1 "register_operand"
 	  "  0, 0,x ,Yv,0,Yv,0,0,v")
 	  (match_operand:DI 2 "nonimmediate_operand"
-	  " jrm,jrm,rm,rm,x,Yv,x,m,m")))]
+	  " jrjm,jrjm,rm,rm,x,Yv,x,m,m")))]
   "TARGET_SSE"
   "@
    pinsrq\t{$1, %2, %0|%0, %2, 1}