[v1] RISC-V: Bugfix PR111362 for incorrect frm emit

From: Pan Li <pan2.li@intel.com>

When the mode switching from NONE to CALL, we will restore the
frm but lack some check if we have static frm insn in cfun.

This patch would like to fix this by adding static frm insn check.

gcc/ChangeLog:

	* PR target/111362
	* config/riscv/riscv.cc (riscv_emit_frm_mode_set): Bugfix.

gcc/testsuite/ChangeLog:

	* PR target/111362
	* gcc.target/riscv/rvv/base/no-honor-frm-1.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/riscv.cc                            |  2 +-
 .../gcc.target/riscv/rvv/base/no-honor-frm-1.c       | 12 ++++++++++++
 2 files changed, 13 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c

LGTM :)

On Wed, Sep 13, 2023 at 2:07 PM Pan Li via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> When the mode switching from NONE to CALL, we will restore the
> frm but lack some check if we have static frm insn in cfun.
>
> This patch would like to fix this by adding static frm insn check.
>
> gcc/ChangeLog:
>
>         * PR target/111362
>         * config/riscv/riscv.cc (riscv_emit_frm_mode_set): Bugfix.
>
> gcc/testsuite/ChangeLog:
>
>         * PR target/111362
>         * gcc.target/riscv/rvv/base/no-honor-frm-1.c: New test.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
>  gcc/config/riscv/riscv.cc                            |  2 +-
>  .../gcc.target/riscv/rvv/base/no-honor-frm-1.c       | 12 ++++++++++++
>  2 files changed, 13 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 9d04ddd69e0..762937b0e37 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -9173,7 +9173,7 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
>        rtx frm = gen_int_mode (mode, SImode);
>
>        if (mode == riscv_vector::FRM_DYN_CALL
> -       && prev_mode != riscv_vector::FRM_DYN)
> +       && prev_mode != riscv_vector::FRM_DYN && STATIC_FRM_P (cfun))
>         /* No need to emit when prev mode is DYN already.  */
>         emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
>        else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
> new file mode 100644
> index 00000000000..b2e0f217bfa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +void foo (void) {
> +  for (unsigned i = 0; i < sizeof(foo); i++)
> +    __builtin_printf("%d", i);
> +}
> +
> +/* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */
> +/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */
> +/* { dg-final { scan-assembler-not {fsrm\s+[axs][0-9]+} } } */
> +/* { dg-final { scan-assembler-not {frrm\s+[axs][0-9]+} } } */
> --
> 2.34.1
>

Committed, thanks Kito.

Pan

-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com> 
Sent: Wednesday, September 13, 2023 2:16 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Bugfix PR111362 for incorrect frm emit

LGTM :)

On Wed, Sep 13, 2023 at 2:07 PM Pan Li via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> When the mode switching from NONE to CALL, we will restore the
> frm but lack some check if we have static frm insn in cfun.
>
> This patch would like to fix this by adding static frm insn check.
>
> gcc/ChangeLog:
>
>         * PR target/111362
>         * config/riscv/riscv.cc (riscv_emit_frm_mode_set): Bugfix.
>
> gcc/testsuite/ChangeLog:
>
>         * PR target/111362
>         * gcc.target/riscv/rvv/base/no-honor-frm-1.c: New test.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
>  gcc/config/riscv/riscv.cc                            |  2 +-
>  .../gcc.target/riscv/rvv/base/no-honor-frm-1.c       | 12 ++++++++++++
>  2 files changed, 13 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 9d04ddd69e0..762937b0e37 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -9173,7 +9173,7 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
>        rtx frm = gen_int_mode (mode, SImode);
>
>        if (mode == riscv_vector::FRM_DYN_CALL
> -       && prev_mode != riscv_vector::FRM_DYN)
> +       && prev_mode != riscv_vector::FRM_DYN && STATIC_FRM_P (cfun))
>         /* No need to emit when prev mode is DYN already.  */
>         emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
>        else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
> new file mode 100644
> index 00000000000..b2e0f217bfa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +void foo (void) {
> +  for (unsigned i = 0; i < sizeof(foo); i++)
> +    __builtin_printf("%d", i);
> +}
> +
> +/* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */
> +/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */
> +/* { dg-final { scan-assembler-not {fsrm\s+[axs][0-9]+} } } */
> +/* { dg-final { scan-assembler-not {frrm\s+[axs][0-9]+} } } */
> --
> 2.34.1
>