From patchwork Thu Sep 7 14:22:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 1830956 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=dgguilAn; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RhM0L3NTzz1ygc for ; Fri, 8 Sep 2023 00:22:58 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 69C633858C20 for ; Thu, 7 Sep 2023 14:22:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 69C633858C20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1694096575; bh=7wwlZBoN86yjk50IyKWGOe+FJBrdxtaSo5sxp8KHhFU=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=dgguilAn/gMgsl+20jOpmyg0dDA0ue33DTdKRoCCR74FiBHj9PFfsmJlOIq1pFv0F bSHotmgB5eH0DY/4IzP5ad/dX++O4ISBwcMVfc1f8FkGZAM8vpwNR9ybfneb/ZLIXa L9k9rhHi5QPrvLMMCuAEekSrd96ObA9aUrJpqQZQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by sourceware.org (Postfix) with ESMTPS id 6CD8F3858D1E for ; Thu, 7 Sep 2023 14:22:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6CD8F3858D1E Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1bee82fad0fso8433965ad.2 for ; Thu, 07 Sep 2023 07:22:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1694096553; x=1694701353; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=7wwlZBoN86yjk50IyKWGOe+FJBrdxtaSo5sxp8KHhFU=; b=RqhDQoVZ7Lmozvx0pPIfaXdJQo7hXyqmTijqrLZ19BAszyUs8bp3gR5rLcSeQpFte9 tIqiMiL0o70XzDfod9NxTNeCzswEM8I5sS6pMgQiETrCADbdU7QmG3A8PgjaeSxyWQic gV1MiqLVOCNIr6WrYG93c2ggJ//UNkDhEwiAguk+aA+YP/SfdWul6QCfy3Ida/wFbahf +3kmUrV+0+H2bnL30hMp8B2c5GhFlS3hs0F/NO1ybKfDoVQIEJ68hWIZDEDoHJv3ZSxh hfBC8qPErY9g6svJcSmsA0WmTyo3wSFu07qe3nQvbA0u+6er/m/QoDnTtRi7mhSk05Fo 3MXQ== X-Gm-Message-State: AOJu0YyGnDkBYKreUPX+RXmRhFOpZgZNmUveWzwiiP0CC5V34hqwYGTO vZ3f2bEcSXtr/6IRSmjmV/ERZKWf7t0= X-Google-Smtp-Source: AGHT+IG1StCHWhGCI2YY69GqnrdAFmuCOu4cJqx28g8nqlVpvzVriWcPS+FXxnne1MQ001u2K1Z+Mw== X-Received: by 2002:a17:902:c38d:b0:1bb:8931:ee94 with SMTP id g13-20020a170902c38d00b001bb8931ee94mr15196066plg.67.1694096553043; Thu, 07 Sep 2023 07:22:33 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:646:a201:19d0:2ac1:f784:1140:83d7]) by smtp.gmail.com with ESMTPSA id jw14-20020a170903278e00b001b9d95945afsm12891167plb.155.2023.09.07.07.22.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Sep 2023 07:22:32 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [RFC] gcc: xtensa: use salt/saltu in xtensa_expand_scc Date: Thu, 7 Sep 2023 07:22:17 -0700 Message-Id: <20230907142217.3753564-1-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-Spam-Status: No, score=-9.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, FROM_LOCAL_NOVOWEL, GIT_PATCH_0, HK_RANDOM_ENVFROM, HK_RANDOM_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Max Filippov via Gcc-patches From: Max Filippov Reply-To: Max Filippov Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" gcc/ * config/xtensa/predicates.md (xtensa_cstoresi_operator): Add unsigned comparisons. * config/xtensa/xtensa.cc (xtensa_expand_scc): Add code generation of salt/saltu instructions. * config/xtensa/xtensa.h (TARGET_SALT): New macro. * gcc/config/xtensa/xtensa.md (salt, saltu): New instruction patterns. --- I've tested it both with configurations that have salt/saltu and that don't. The inversion of the result at the end looks wasteful. I've been reading gccint chapter about cstoreMODE4 and the following part left me with the question: The value stored for a true condition must have 1 as its low bit, or else must be negative. Does it mean that some variants of cstoreMODE4 may return 1 and some may return -1 for truth, as both have 1 as its low bit? If that's true we could use 'addi dest, dest, -1' instead of two-intruction sequence 'movi tmp, 1; xor dest, dest, tmp'. --- gcc/config/xtensa/predicates.md | 2 +- gcc/config/xtensa/xtensa.cc | 58 +++++++++++++++++++++++++++++++++ gcc/config/xtensa/xtensa.h | 1 + gcc/config/xtensa/xtensa.md | 20 ++++++++++++ 4 files changed, 80 insertions(+), 1 deletion(-) diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md index a3575a688923..672fb003a6c5 100644 --- a/gcc/config/xtensa/predicates.md +++ b/gcc/config/xtensa/predicates.md @@ -195,7 +195,7 @@ (match_code "plus,minus")) (define_predicate "xtensa_cstoresi_operator" - (match_code "eq,ne,gt,ge,lt,le")) + (match_code "eq,ne,gt,ge,lt,le,gtu,geu,ltu,leu")) (define_predicate "xtensa_shift_per_byte_operator" (match_code "ashift,ashiftrt,lshiftrt")) diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc index 1afaa1cc94e7..cc63529e80ea 100644 --- a/gcc/config/xtensa/xtensa.cc +++ b/gcc/config/xtensa/xtensa.cc @@ -1028,6 +1028,64 @@ xtensa_expand_scc (rtx operands[4], machine_mode cmp_mode) break; } + if (cmp_mode == SImode && TARGET_SALT) + { + bool swap_args = false; + bool invert_res = false; + rtx a = operands[2], b = force_reg (SImode, operands[3]); + + switch (code) + { + case GE: + case GEU: + invert_res = true; + break; + case GT: + case GTU: + swap_args = true; + break; + case LE: + case LEU: + invert_res = true; + swap_args = true; + break; + default: + break; + } + + if (swap_args) + std::swap (a, b); + + switch (code) + { + case GE: + case GT: + case LE: + case LT: + emit_insn (gen_salt (dest, a, b)); + if (!invert_res) + return 1; + break; + case GEU: + case GTU: + case LEU: + case LTU: + emit_insn (gen_saltu (dest, a, b)); + if (!invert_res) + return 1; + break; + default: + break; + } + + if (invert_res) + { + one_tmp = force_reg (SImode, const1_rtx); + emit_insn (gen_xorsi3 (dest, dest, one_tmp)); + return 1; + } + } + if (! (cmp = gen_conditional_move (code, cmp_mode, operands[2], operands[3]))) return 0; diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h index 34e06afcff48..5987681e5496 100644 --- a/gcc/config/xtensa/xtensa.h +++ b/gcc/config/xtensa/xtensa.h @@ -54,6 +54,7 @@ along with GCC; see the file COPYING3. If not see #define TARGET_WINDOWED_ABI xtensa_windowed_abi #define TARGET_DEBUG XCHAL_HAVE_DEBUG #define TARGET_L32R XCHAL_HAVE_L32R +#define TARGET_SALT (XTENSA_MARCH_EARLIEST >= 260000) #define TARGET_DEFAULT (MASK_SERIALIZE_VOLATILE) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index d6505e7eb700..594238030237 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -2393,6 +2393,26 @@ DONE; }) +(define_insn "salt" + [(set (match_operand:SI 0 "register_operand" "=a") + (lt:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")))] + "TARGET_SALT" + "salt\t%0, %1, %2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "3")]) + +(define_insn "saltu" + [(set (match_operand:SI 0 "register_operand" "=a") + (ltu:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")))] + "TARGET_SALT" + "saltu\t%0, %1, %2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "3")]) + (define_expand "cstoresf4" [(match_operand:SI 0 "register_operand") (match_operator:SI 1 "comparison_operator"