From patchwork Mon Sep 4 09:08:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 1829394 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RfN9b6ckWz1ynq for ; Mon, 4 Sep 2023 19:09:07 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4AC183858017 for ; Mon, 4 Sep 2023 09:09:05 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgau2.qq.com (smtpbgau2.qq.com [54.206.34.216]) by sourceware.org (Postfix) with ESMTPS id B3E9E3858D3C for ; Mon, 4 Sep 2023 09:08:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B3E9E3858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp76t1693818517txknn9hb Received: from server1.localdomain ( [58.60.1.8]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 04 Sep 2023 17:08:36 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: cvpDInk2tjXraYBs962R7QvbqJuR4D2Q+eh6I73ihUP9dtPnQwqqY7cufJeU8 H4E6QlGf1w1y1VdCMqfG2TmIWv3qlIXzRR/pCi/7eu5w8xqvg2MsrZgwFAoHNJdFl8BmkUR kK+tYz8c9ISMz8Weq7sgFPOt2TUFmEbmQTpsflyZSCku30/Zdgp+BpDepZGuB0VdxPtz4e7 JwBp0EWLNLh8lSU4nQINhPgDYPFTAZPQROwXxDm33asLNXlIK0IAy6iTXNLHACaGY+XHLVD zS4KQya+P8slb6RBcC0Y1tRZZgDWFtIoYqqWMyYBhUEIgEIe0Ogw0miIdgLkaWWlHQ4UzQV zgeFhxkjzABs3rwKlzbo2QiY+FBo0ZUQs7UUpftclw6EehPAW07BWsJ2GO+UBI0CMvfvRxV l91PXlshHUCGU6am6SaMWA== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 12151012381601074450 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Fix Dynamic LMUL compile option Date: Mon, 4 Sep 2023 17:08:34 +0800 Message-Id: <20230904090834.148723-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@sifive.com, kito.cheng@gmail.com, Juzhe-Zhong Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" gcc/ChangeLog: * config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Fix Dynamic status. * config/riscv/riscv-v.cc (preferred_simd_mode): Ditto. (autovectorize_vector_modes): Ditto. (vectorize_related_mode): Ditto. --- gcc/config/riscv/riscv-opts.h | 2 +- gcc/config/riscv/riscv-v.cc | 15 ++++++++------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 79e0f12e388..b6b5907e111 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -81,7 +81,7 @@ enum riscv_autovec_lmul_enum { RVV_M4 = 4, RVV_M8 = 8, /* For dynamic LMUL, we compare COST start with LMUL8. */ - RVV_DYNAMIC = RVV_M8 + RVV_DYNAMIC = 9 }; enum riscv_multilib_select_kind { diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index c8ad96f44d5..fbbc16a3c26 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1971,16 +1971,16 @@ preferred_simd_mode (scalar_mode mode) vectorizer when we enable them in this target hook. Currently, we can support auto-vectorization in -march=rv32_zve32x_zvl128b. Wheras, -march=rv32_zve32x_zvl32b or -march=rv32_zve32x_zvl64b are disabled. */ + int lmul = riscv_autovec_lmul == RVV_DYNAMIC ? RVV_M8 : riscv_autovec_lmul; if (autovec_use_vlmax_p ()) { - if (TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2) + if (TARGET_MIN_VLEN < 128 && lmul < RVV_M2) return word_mode; /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and riscv_autovec_lmul as multiply factor to calculate the the NUNITS to get the auto-vectorization mode. */ poly_uint64 nunits; - poly_uint64 vector_size - = BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul); + poly_uint64 vector_size = BYTES_PER_RISCV_VECTOR * lmul; poly_uint64 scalar_size = GET_MODE_SIZE (mode); gcc_assert (multiple_p (vector_size, scalar_size, &nunits)); machine_mode rvv_mode; @@ -2154,10 +2154,10 @@ get_cmp_insn_code (rtx_code code, machine_mode mode) unsigned int autovectorize_vector_modes (vector_modes *modes, bool) { + int lmul = riscv_autovec_lmul == RVV_DYNAMIC ? RVV_M8 : riscv_autovec_lmul; if (autovec_use_vlmax_p ()) { - poly_uint64 full_size - = BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul); + poly_uint64 full_size = BYTES_PER_RISCV_VECTOR * lmul; /* Start with a RVVQImode where LMUL is the number of units that fit a whole vector. @@ -2187,7 +2187,7 @@ autovectorize_vector_modes (vector_modes *modes, bool) { /* Push all VLSmodes according to TARGET_MIN_VLEN. */ unsigned int i = 0; - unsigned int base_size = TARGET_MIN_VLEN * riscv_autovec_lmul / 8; + unsigned int base_size = TARGET_MIN_VLEN * lmul / 8; unsigned int size = base_size; machine_mode mode; while (size > 0 && get_vector_mode (QImode, size).exists (&mode)) @@ -2212,8 +2212,9 @@ vectorize_related_mode (machine_mode vector_mode, scalar_mode element_mode, { /* TODO: We will support RVV VLS auto-vectorization mode in the future. */ poly_uint64 min_units; + int lmul = riscv_autovec_lmul == RVV_DYNAMIC ? RVV_M8 : riscv_autovec_lmul; if (autovec_use_vlmax_p () && riscv_v_ext_vector_mode_p (vector_mode) - && multiple_p (BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul), + && multiple_p (BYTES_PER_RISCV_VECTOR * lmul, GET_MODE_SIZE (element_mode), &min_units)) { machine_mode rvv_mode;