From patchwork Tue Aug 29 02:36:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 1827060 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RZWm60HkDz1yZ9 for ; Tue, 29 Aug 2023 12:37:08 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6706E38582B0 for ; Tue, 29 Aug 2023 02:37:06 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by sourceware.org (Postfix) with ESMTPS id 30E753858D28 for ; Tue, 29 Aug 2023 02:36:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 30E753858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp76t1693276604tsi76zck Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 29 Aug 2023 10:36:43 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: +ynUkgUhZJlysNTptEwlvPbKkh3tpMvPFMhDpVtNeeGW98ZSL7PUG3l9SK3zO Kv6b7njd5ZV7QAocf+bwBuiGILOK8P150qAhE5wwoqhmwov294ZYl9uLw2D4xXAzZoc7Xv2 sV8Qc6CuhPtIBOvB/0EYWuS4GBmeuGm3S9Zj9EcLKniria/wK1TC2DAW8N5Gm6JruYlkz4y ITEgK5s1OF819Qe8KnfyHrjq6OwFRxWhjoxKsT7dG9BpFZ3fZkH1S2Pg9BOV378PkGeApq+ TWa8tfQAGMTeb0We2w13tos3Ls35xug9J99UxZO6uKOZvJ51ZrOlWcr3LozpopoCoyaX/p8 QG+449eJt+KyOiHhJ4g9hj2uNXrK2gUwg5uR9vxe1DcKBP5bI45BX1h5ztXQJDXL+wcrhGf X-QQ-GoodBg: 2 X-BIZMAIL-ID: 13223209266300238844 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Fix AVL/VL get ICE[VSETVL PASS] Date: Tue, 29 Aug 2023 10:36:42 +0800 Message-Id: <20230829023642.154907-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@sifive.com, kito.cheng@gmail.com, Juzhe-Zhong Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Fix bunch of ICE in "vect" testsuite: FAIL: gcc.dg/vect/vect-alias-check-16.c (internal compiler error: Segmentation fault) FAIL: gcc.dg/vect/vect-alias-check-16.c (test for excess errors) FAIL: gcc.dg/vect/vect-alias-check-16.c -flto -ffat-lto-objects (internal compiler error: Segmentation fault) FAIL: gcc.dg/vect/vect-alias-check-16.c -flto -ffat-lto-objects (test for excess errors) FAIL: gcc.dg/vect/vect-alias-check-20.c (internal compiler error: Segmentation fault) FAIL: gcc.dg/vect/vect-alias-check-20.c (test for excess errors) FAIL: gcc.dg/vect/vect-alias-check-20.c -flto -ffat-lto-objects (internal compiler error: Segmentation fault) FAIL: gcc.dg/vect/vect-alias-check-20.c -flto -ffat-lto-objects (test for excess errors) gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (vector_insn_info::get_avl_or_vl_reg): New function. (pass_vsetvl::compute_local_properties): Fix bug. (pass_vsetvl::commit_vsetvls): Ditto. * config/riscv/riscv-vsetvl.h: New function. --- gcc/config/riscv/riscv-vsetvl.cc | 46 +++++++++++++++++++++----------- gcc/config/riscv/riscv-vsetvl.h | 1 + 2 files changed, 31 insertions(+), 16 deletions(-) diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index f7ae6c16bee..73d672b083b 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -2290,6 +2290,32 @@ vector_insn_info::global_merge (const vector_insn_info &merge_info, return new_info; } +/* Wrapper helps to return the AVL or VL operand for the + vector_insn_info. Return AVL if the AVL is not VLMAX. + Otherwise, return the VL operand. */ +rtx +vector_insn_info::get_avl_or_vl_reg (void) const +{ + gcc_assert (has_avl_reg ()); + if (!vlmax_avl_p (get_avl ())) + return get_avl (); + + if (has_vl_op (get_insn ()->rtl ()) || vsetvl_insn_p (get_insn ()->rtl ())) + return ::get_vl (get_insn ()->rtl ()); + + if (get_avl_source ()) + return get_avl_reg_rtx (); + + /* A DIRTY (polluted EMPTY) block if: + - get_insn is scalar move (no AVL or VL operand). + - get_avl_source is null (no def in the current DIRTY block). + Then we trace the previous insn which must be the insn + already inserted in Phase 2 to get the VL operand for VLMAX. */ + rtx_insn *prev_rinsn = PREV_INSN (get_insn ()->rtl ()); + gcc_assert (prev_rinsn && vsetvl_insn_p (prev_rinsn)); + return ::get_vl (prev_rinsn); +} + bool vector_insn_info::update_fault_first_load_avl (insn_info *insn) { @@ -3166,19 +3192,17 @@ pass_vsetvl::compute_local_properties (void) bitmap_clear_bit (m_vector_manager->vector_transp[curr_bb_idx], i); else if (expr->has_avl_reg ()) { - rtx avl = vlmax_avl_p (expr->get_avl ()) - ? get_vl (expr->get_insn ()->rtl ()) - : expr->get_avl (); + rtx reg = expr->get_avl_or_vl_reg (); for (const insn_info *insn : bb->real_nondebug_insns ()) { - if (find_access (insn->defs (), REGNO (avl))) + if (find_access (insn->defs (), REGNO (reg))) { bitmap_clear_bit ( m_vector_manager->vector_transp[curr_bb_idx], i); break; } else if (vlmax_avl_p (expr->get_avl ()) - && find_access (insn->uses (), REGNO (avl))) + && find_access (insn->uses (), REGNO (reg))) { bitmap_clear_bit ( m_vector_manager->vector_transp[curr_bb_idx], i); @@ -3649,17 +3673,7 @@ pass_vsetvl::commit_vsetvls (void) = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, reaching_out, NULL_RTX); else if (vlmax_avl_p (reaching_out.get_avl ())) { - rtx vl = NULL_RTX; - /* For user VSETVL VL, AVL. We need to use VL operand here, so we - don't directly use get_avl_reg_rtx (). Instead, we use the VL - of the INSN->RTL (). */ - if (!reaching_out.get_avl_source ()) - { - gcc_assert (vsetvl_insn_p (reaching_out.get_insn ()->rtl ())); - vl = get_vl (reaching_out.get_insn ()->rtl ()); - } - else - vl = reaching_out.get_avl_reg_rtx (); + rtx vl = reaching_out.get_avl_or_vl_reg (); new_pat = gen_vsetvl_pat (VSETVL_NORMAL, reaching_out, vl); } else diff --git a/gcc/config/riscv/riscv-vsetvl.h b/gcc/config/riscv/riscv-vsetvl.h index 4b5825d7f6b..2a315e45f31 100644 --- a/gcc/config/riscv/riscv-vsetvl.h +++ b/gcc/config/riscv/riscv-vsetvl.h @@ -335,6 +335,7 @@ public: rtl_ssa::insn_info *get_insn () const { return m_insn; } const bool *get_demands (void) const { return m_demands; } + rtx get_avl_or_vl_reg (void) const; rtx get_avl_reg_rtx (void) const { return gen_rtx_REG (Pmode, get_avl_source ()->regno ());