diff mbox series

RISC-V: Fix incorrect VTYPE fusion for floating point scalar move insn[PR111037]

Message ID 20230817055906.2843802-1-juzhe.zhong@rivai.ai
State New
Headers show
Series RISC-V: Fix incorrect VTYPE fusion for floating point scalar move insn[PR111037] | expand

Commit Message

juzhe.zhong@rivai.ai Aug. 17, 2023, 5:59 a.m. UTC 
void foo(_Float16 y, int64_t *i64p)
{
  vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1);
  vx = __riscv_vadd_vv_i64m1 (vx, vx, 1);
  vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1);
  asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy));
}

zve64f:
foo:
	vsetivli	zero,1,e16,mf4,ta,ma
	vle64.v	v1,0(a0)
	vfmv.s.f	v2,fa0
	vsetvli	zero,zero,e64,m1,ta,ma
	vadd.vv	v1,v1,v1

zve64d:
foo:
	vsetivli	zero,1,e64,m1,ta,ma
	vle64.v	v1,0(a0)
	vfmv.s.f	v2,fa0
	vadd.vv	v1,v1,v1

        PR target111037

gcc/ChangeLog:

        * config/riscv/riscv-vsetvl.cc (float_insn_valid_sew_p): New function.
        (second_sew_less_than_first_sew_p): Fix bug.
        (first_sew_less_than_second_sew_p): Ditto.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/pr111037-1.c: New test.
        * gcc.target/riscv/rvv/base/pr111037-2.c: New test.

---
 gcc/config/riscv/riscv-vsetvl.cc              | 22 +++++++++++++++++--
 .../gcc.target/riscv/rvv/base/pr111037-1.c    | 15 +++++++++++++
 .../gcc.target/riscv/rvv/base/pr111037-2.c    |  8 +++++++
 3 files changed, 43 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c

Comments

Kito Cheng Aug. 17, 2023, 6:07 a.m. UTC | #1 
LGTM, thanks :)

On Thu, Aug 17, 2023 at 1:59 PM Juzhe-Zhong <juzhe.zhong@rivai.ai> wrote:
>
> void foo(_Float16 y, int64_t *i64p)
> {
>   vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1);
>   vx = __riscv_vadd_vv_i64m1 (vx, vx, 1);
>   vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1);
>   asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy));
> }
>
> zve64f:
> foo:
>         vsetivli        zero,1,e16,mf4,ta,ma
>         vle64.v v1,0(a0)
>         vfmv.s.f        v2,fa0
>         vsetvli zero,zero,e64,m1,ta,ma
>         vadd.vv v1,v1,v1
>
> zve64d:
> foo:
>         vsetivli        zero,1,e64,m1,ta,ma
>         vle64.v v1,0(a0)
>         vfmv.s.f        v2,fa0
>         vadd.vv v1,v1,v1
>
>         PR target111037
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-vsetvl.cc (float_insn_valid_sew_p): New function.
>         (second_sew_less_than_first_sew_p): Fix bug.
>         (first_sew_less_than_second_sew_p): Ditto.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/base/pr111037-1.c: New test.
>         * gcc.target/riscv/rvv/base/pr111037-2.c: New test.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc              | 22 +++++++++++++++++--
>  .../gcc.target/riscv/rvv/base/pr111037-1.c    | 15 +++++++++++++
>  .../gcc.target/riscv/rvv/base/pr111037-2.c    |  8 +++++++
>  3 files changed, 43 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
> index 08c487d82c0..79cbac01047 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -1183,18 +1183,36 @@ second_ratio_invalid_for_first_lmul_p (const vector_insn_info &info1,
>    return calculate_sew (info1.get_vlmul (), info2.get_ratio ()) == 0;
>  }
>
> +static bool
> +float_insn_valid_sew_p (const vector_insn_info &info, unsigned int sew)
> +{
> +  if (info.get_insn () && info.get_insn ()->is_real ()
> +      && get_attr_type (info.get_insn ()->rtl ()) == TYPE_VFMOVFV)
> +    {
> +      if (sew == 16)
> +       return TARGET_VECTOR_ELEN_FP_16;
> +      else if (sew == 32)
> +       return TARGET_VECTOR_ELEN_FP_32;
> +      else if (sew == 64)
> +       return TARGET_VECTOR_ELEN_FP_64;
> +    }
> +  return true;
> +}
> +
>  static bool
>  second_sew_less_than_first_sew_p (const vector_insn_info &info1,
>                                   const vector_insn_info &info2)
>  {
> -  return info2.get_sew () < info1.get_sew ();
> +  return info2.get_sew () < info1.get_sew ()
> +        || !float_insn_valid_sew_p (info1, info2.get_sew ());
>  }
>
>  static bool
>  first_sew_less_than_second_sew_p (const vector_insn_info &info1,
>                                   const vector_insn_info &info2)
>  {
> -  return info1.get_sew () < info2.get_sew ();
> +  return info1.get_sew () < info2.get_sew ()
> +        || !float_insn_valid_sew_p (info2, info1.get_sew ());
>  }
>
>  /* return 0 if LMUL1 == LMUL2.
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c
> new file mode 100644
> index 00000000000..0b7b32fc3e6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +void foo(_Float16 y, int64_t *i64p)
> +{
> +  vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1);
> +  vx = __riscv_vadd_vv_i64m1 (vx, vx, 1);
> +  vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1);
> +  asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy));
> +}
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c
> new file mode 100644
> index 00000000000..ac50da71726
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c
> @@ -0,0 +1,8 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */
> +
> +#include "pr111037-1.c"
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */
> +/* { dg-final { scan-assembler-not {vsetvli} } } */
> +/* { dg-final { scan-assembler-times {vsetivli} 1 } } */
> --
> 2.36.3
>
Li, Pan2 via Gcc-patches Aug. 17, 2023, 6:21 a.m. UTC | #2 
Committed, thanks Kito.

Pan

-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Kito Cheng via Gcc-patches
Sent: Thursday, August 17, 2023 2:08 PM
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Cc: gcc-patches@gcc.gnu.org; kito.cheng@sifive.com; jeffreyalaw@gmail.com; rdapp.gcc@gmail.com
Subject: Re: [PATCH] RISC-V: Fix incorrect VTYPE fusion for floating point scalar move insn[PR111037]

LGTM, thanks :)

On Thu, Aug 17, 2023 at 1:59 PM Juzhe-Zhong <juzhe.zhong@rivai.ai> wrote:
>
> void foo(_Float16 y, int64_t *i64p)
> {
>   vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1);
>   vx = __riscv_vadd_vv_i64m1 (vx, vx, 1);
>   vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1);
>   asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy));
> }
>
> zve64f:
> foo:
>         vsetivli        zero,1,e16,mf4,ta,ma
>         vle64.v v1,0(a0)
>         vfmv.s.f        v2,fa0
>         vsetvli zero,zero,e64,m1,ta,ma
>         vadd.vv v1,v1,v1
>
> zve64d:
> foo:
>         vsetivli        zero,1,e64,m1,ta,ma
>         vle64.v v1,0(a0)
>         vfmv.s.f        v2,fa0
>         vadd.vv v1,v1,v1
>
>         PR target111037
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-vsetvl.cc (float_insn_valid_sew_p): New function.
>         (second_sew_less_than_first_sew_p): Fix bug.
>         (first_sew_less_than_second_sew_p): Ditto.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/base/pr111037-1.c: New test.
>         * gcc.target/riscv/rvv/base/pr111037-2.c: New test.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc              | 22 +++++++++++++++++--
>  .../gcc.target/riscv/rvv/base/pr111037-1.c    | 15 +++++++++++++
>  .../gcc.target/riscv/rvv/base/pr111037-2.c    |  8 +++++++
>  3 files changed, 43 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
> index 08c487d82c0..79cbac01047 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -1183,18 +1183,36 @@ second_ratio_invalid_for_first_lmul_p (const vector_insn_info &info1,
>    return calculate_sew (info1.get_vlmul (), info2.get_ratio ()) == 0;
>  }
>
> +static bool
> +float_insn_valid_sew_p (const vector_insn_info &info, unsigned int sew)
> +{
> +  if (info.get_insn () && info.get_insn ()->is_real ()
> +      && get_attr_type (info.get_insn ()->rtl ()) == TYPE_VFMOVFV)
> +    {
> +      if (sew == 16)
> +       return TARGET_VECTOR_ELEN_FP_16;
> +      else if (sew == 32)
> +       return TARGET_VECTOR_ELEN_FP_32;
> +      else if (sew == 64)
> +       return TARGET_VECTOR_ELEN_FP_64;
> +    }
> +  return true;
> +}
> +
>  static bool
>  second_sew_less_than_first_sew_p (const vector_insn_info &info1,
>                                   const vector_insn_info &info2)
>  {
> -  return info2.get_sew () < info1.get_sew ();
> +  return info2.get_sew () < info1.get_sew ()
> +        || !float_insn_valid_sew_p (info1, info2.get_sew ());
>  }
>
>  static bool
>  first_sew_less_than_second_sew_p (const vector_insn_info &info1,
>                                   const vector_insn_info &info2)
>  {
> -  return info1.get_sew () < info2.get_sew ();
> +  return info1.get_sew () < info2.get_sew ()
> +        || !float_insn_valid_sew_p (info2, info1.get_sew ());
>  }
>
>  /* return 0 if LMUL1 == LMUL2.
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c
> new file mode 100644
> index 00000000000..0b7b32fc3e6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +void foo(_Float16 y, int64_t *i64p)
> +{
> +  vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1);
> +  vx = __riscv_vadd_vv_i64m1 (vx, vx, 1);
> +  vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1);
> +  asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy));
> +}
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c
> new file mode 100644
> index 00000000000..ac50da71726
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c
> @@ -0,0 +1,8 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */
> +
> +#include "pr111037-1.c"
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */
> +/* { dg-final { scan-assembler-not {vsetvli} } } */
> +/* { dg-final { scan-assembler-times {vsetivli} 1 } } */
> --
> 2.36.3
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 08c487d82c0..79cbac01047 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1183,18 +1183,36 @@  second_ratio_invalid_for_first_lmul_p (const vector_insn_info &info1,
   return calculate_sew (info1.get_vlmul (), info2.get_ratio ()) == 0;
 }
 
+static bool
+float_insn_valid_sew_p (const vector_insn_info &info, unsigned int sew)
+{
+  if (info.get_insn () && info.get_insn ()->is_real ()
+      && get_attr_type (info.get_insn ()->rtl ()) == TYPE_VFMOVFV)
+    {
+      if (sew == 16)
+	return TARGET_VECTOR_ELEN_FP_16;
+      else if (sew == 32)
+	return TARGET_VECTOR_ELEN_FP_32;
+      else if (sew == 64)
+	return TARGET_VECTOR_ELEN_FP_64;
+    }
+  return true;
+}
+
 static bool
 second_sew_less_than_first_sew_p (const vector_insn_info &info1,
 				  const vector_insn_info &info2)
 {
-  return info2.get_sew () < info1.get_sew ();
+  return info2.get_sew () < info1.get_sew ()
+	 || !float_insn_valid_sew_p (info1, info2.get_sew ());
 }
 
 static bool
 first_sew_less_than_second_sew_p (const vector_insn_info &info1,
 				  const vector_insn_info &info2)
 {
-  return info1.get_sew () < info2.get_sew ();
+  return info1.get_sew () < info2.get_sew ()
+	 || !float_insn_valid_sew_p (info2, info1.get_sew ());
 }
 
 /* return 0 if LMUL1 == LMUL2.
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c
new file mode 100644
index 00000000000..0b7b32fc3e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
+
+#include "riscv_vector.h"
+
+void foo(_Float16 y, int64_t *i64p)
+{
+  vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1);
+  vx = __riscv_vadd_vv_i64m1 (vx, vx, 1);
+  vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1);
+  asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy));
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c
new file mode 100644
index 00000000000..ac50da71726
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c
@@ -0,0 +1,8 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */
+
+#include "pr111037-1.c"
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 } } */