From patchwork Sat Aug 12 14:15:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 1820576 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RNN466Z6pz1yf6 for ; Sun, 13 Aug 2023 00:15:49 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 48BB73858C33 for ; Sat, 12 Aug 2023 14:15:46 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id 9B5593858D20 for ; Sat, 12 Aug 2023 14:15:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9B5593858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp83t1691849718tvmhbky0 Received: from server1.localdomain ( [58.60.1.10]) by bizesmtp.qq.com (ESMTP) with id ; Sat, 12 Aug 2023 22:15:17 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: W+onFc5Tw4MKj/Xt7gTeo/ZucPn3rcQEqKK9UbW0t+bWf7nH8c61f4apDnCMZ yjU+4zvYSQGaWxnNRDrhngWpE0Db/yqq6ltWPK+94sqUVlPf18XRTde3ySDY65Af/F8nEXP zicZWExLx4G0hSAZ2Jz7jOmyr9PDOI8B1gRVax4e5uRT7aSanN5A6V91ACSyVCt7pskzMW/ QnczWxrqDOaLuUmRsRryCUHKVb7CyRUxQHorNMklJr0obt48x/UuXGvaABbEnGot5qyGkYc 9omDUA3pd9YYXXCGI9ZgkRI4IhymOPAucMDQF3GE3Y8DHh632RXFaskat1WyUv8KGb4hmpZ +0vxzke47zchRM3XyMENHDsFsfDhgD+eMFjoTN54r3yUg3cj56OrrAM2St48Rpj0Yz+Dfyk X-QQ-GoodBg: 2 X-BIZMAIL-ID: 16203148983500084656 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, kito.cheng@gmail.com, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix autovec_length_operand predicate[PR110989] Date: Sat, 12 Aug 2023 22:15:15 +0800 Message-Id: <20230812141515.326096-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Currently, autovec_length_operand predicate incorrect configuration is discovered in PR110989 since this following situation: vect__6.24_107 = .MASK_LEN_LOAD (vectp.22_105, 32B, mask__49.21_99, POLY_INT_CST [2, 2], 0); ---> dummy length = VF. The current autovec length operand failed to recognize the VF dummy length. -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2: Before this patch: srli a4,s0,2 addi a4,a4,-3 srli s0,s0,3 vsetvli a5,zero,e64,m1,ta,ma vid.v v1 vmul.vx v1,v1,a4 addi a4,s0,-2 vadd.vx v1,v1,a4 addi a4,s0,-1 vslide1up.vx v2,v1,a4 vmv.v.x v1,a4 vand.vv v1,v2,v1 vl1re64.v v3,0(t2) vrgather.vv v2,v3,v1 vmv.v.i v1,0 vmfeq.vv v0,v2,v1 vsetvli zero,s0,e32,mf2,ta,ma ---> s0 = POLY (2,2) vle32.v v3,0(t3),v0.t vsetvli a5,zero,e64,m1,ta,ma vmfne.vv v0,v2,v1 vsetvli zero,zero,e32,mf2,ta,ma vfwcvt.f.x.v v1,v3 vsetvli zero,zero,e64,m1,ta,ma vmerge.vvm v1,v1,v2,v0 vslidedown.vx v1,v1,a4 vfmv.f.s fa5,v1 j .L6 After this patch: srli a4,s0,2 addi a4,a4,-3 srli s0,s0,3 vsetvli a5,zero,e64,m1,ta,ma vid.v v1 vmul.vx v1,v1,a4 addi a4,s0,-2 vadd.vx v1,v1,a4 addi s0,s0,-1 vslide1up.vx v2,v1,s0 vmv.v.x v1,s0 vand.vv v1,v2,v1 vl1re64.v v3,0(t2) vrgather.vv v2,v3,v1 vmv.v.i v1,0 vmfeq.vv v0,v2,v1 vle32.v v3,0(t3),v0.t vmfne.vv v0,v2,v1 vsetvli zero,zero,e32,mf2,ta,ma vfwcvt.f.x.v v1,v3 vsetvli zero,zero,e64,m1,ta,ma vmerge.vvm v1,v1,v2,v0 vslidedown.vx v1,v1,s0 vfmv.f.s fa5,v1 j .L6 2 vsetvli insns are reduced. gcc/ChangeLog: * config/riscv/predicates.md: Fix predicate. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr110989.c: Add vsetvli assembly check. --- gcc/config/riscv/predicates.md | 5 +---- gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c | 7 ++++++- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 9db28c2def7..b6ebdcf55de 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -282,10 +282,7 @@ (define_special_predicate "autovec_length_operand" (ior (match_operand 0 "pmode_register_operand") - (ior (match_operand 0 "const_csr_operand") - (match_test "rtx_equal_p (op, gen_int_mode - (GET_MODE_NUNITS (GET_MODE (op)), - Pmode))")))) + (match_code "const_int,const_poly_int"))) (define_predicate "reg_or_mem_operand" (ior (match_operand 0 "register_operand") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c index cf3b247e604..6e163a55c56 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */ int a, b, c; double *d; @@ -9,3 +9,8 @@ void e() { f = *d ?: *(&a + c); b = f; } + +/* { dg-final { scan-assembler-times {vsetvli} 3 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 } } */