From patchwork Tue Jul 11 03:13:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 1806158 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=yNdhRl/X; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R0Qvm6mwZz20b9 for ; Tue, 11 Jul 2023 13:14:28 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2C1493858C3A for ; Tue, 11 Jul 2023 03:14:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2C1493858C3A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689045266; bh=duqVFjjn2bSmRQoxYAPW2eXHy3TDVaHaTsw1Gt3m860=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=yNdhRl/XXzUC8HnIV822tlYIY76lRslBtaNxNMBB1E78d4knhIjEXaXfHnnn5BKuH T8nPBR2+58itrJ2qsVdpQF1WYQAvLxYO8Bdyzr7LCoRk3E5TCi2ilSXRYTZeFANEi0 fVCurFgRajfyuN9Oy7/J1D6+Sxa5NktaI4L4XFFc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id F056C3858CDA for ; Tue, 11 Jul 2023 03:14:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F056C3858CDA X-IronPort-AV: E=McAfee;i="6600,9927,10767"; a="349317940" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="349317940" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2023 20:13:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10767"; a="895015747" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="895015747" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga005.jf.intel.com with ESMTP; 10 Jul 2023 20:13:56 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 433D51005043; Tue, 11 Jul 2023 11:13:56 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com Subject: [PATCH] Add peephole to eliminate redundant comparison after cmpccxadd. Date: Tue, 11 Jul 2023 11:13:56 +0800 Message-Id: <20230711031356.3066611-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.39.1.388.g2fc9e9ca3c MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Similar like we did for cmpxchg, but extended to all ix86_comparison_int_operator since cmpccxadd set EFLAGS exactly same as CMP. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}, Ok for trunk? gcc/ChangeLog: PR target/110591 * config/i386/sync.md (cmpccxadd_): Add a new define_peephole2 after the pattern. gcc/testsuite/ChangeLog: * gcc.target/i386/pr110591.c: New test. --- gcc/config/i386/sync.md | 56 ++++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr110591.c | 66 ++++++++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr110591.c diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index e1fa1504deb..43f6421bcb8 100644 --- a/gcc/config/i386/sync.md +++ b/gcc/config/i386/sync.md @@ -1105,3 +1105,59 @@ (define_insn "cmpccxadd_" output_asm_insn (buf, operands); return ""; }) + +(define_peephole2 + [(set (match_operand:SWI48x 0 "register_operand") + (match_operand:SWI48x 1 "x86_64_general_operand")) + (parallel [(set (match_dup 0) + (unspec_volatile:SWI48x + [(match_operand:SWI48x 2 "memory_operand") + (match_dup 0) + (match_operand:SWI48x 3 "register_operand") + (match_operand:SI 4 "const_int_operand")] + UNSPECV_CMPCCXADD)) + (set (match_dup 2) + (unspec_volatile:SWI48x [(const_int 0)] UNSPECV_CMPCCXADD)) + (clobber (reg:CC FLAGS_REG))]) + (set (reg FLAGS_REG) + (compare (match_operand:SWI48x 5 "register_operand") + (match_operand:SWI48x 6 "x86_64_general_operand"))) + (set (match_operand:QI 7 "nonimmediate_operand") + (match_operator:QI 8 "ix86_comparison_int_operator" + [(reg FLAGS_REG) (const_int 0)]))] + "TARGET_CMPCCXADD && TARGET_64BIT + && ((rtx_equal_p (operands[0], operands[5]) + && rtx_equal_p (operands[1], operands[6])) + || ((rtx_equal_p (operands[0], operands[6]) + && rtx_equal_p (operands[1], operands[5])) + && peep2_regno_dead_p (4, FLAGS_REG)))" + [(set (match_dup 0) + (match_dup 1)) + (parallel [(set (match_dup 0) + (unspec_volatile:SWI48x + [(match_dup 2) + (match_dup 0) + (match_dup 3) + (match_dup 4)] + UNSPECV_CMPCCXADD)) + (set (match_dup 2) + (unspec_volatile:SWI48x [(const_int 0)] UNSPECV_CMPCCXADD)) + (clobber (reg:CC FLAGS_REG))]) + (set (match_dup 7) + (match_op_dup 8 + [(match_dup 9) (const_int 0)]))] +{ + operands[9] = gen_rtx_REG (GET_MODE (XEXP (operands[8], 0)), FLAGS_REG); + if (rtx_equal_p (operands[0], operands[6]) + && rtx_equal_p (operands[1], operands[5]) + && swap_condition (GET_CODE (operands[8])) != GET_CODE (operands[8])) + { + operands[8] = shallow_copy_rtx (operands[8]); + enum rtx_code ccode = swap_condition (GET_CODE (operands[8])); + PUT_CODE (operands[8], ccode); + operands[9] = gen_rtx_REG (SELECT_CC_MODE (ccode, + operands[6], + operands[5]), + FLAGS_REG); + } +}) diff --git a/gcc/testsuite/gcc.target/i386/pr110591.c b/gcc/testsuite/gcc.target/i386/pr110591.c new file mode 100644 index 00000000000..32a515b429e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr110591.c @@ -0,0 +1,66 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mcmpccxadd -O2" } */ +/* { dg-final { scan-assembler-not {cmp[lq]?[ \t]+} } } */ +/* { dg-final { scan-assembler-times {cmpoxadd[ \t]+} 12 } } */ + +#include + +_Bool foo_setg (int *ptr, int v) +{ + return _cmpccxadd_epi32(ptr, v, 1, _CMPCCX_O) > v; +} + +_Bool foo_setl (int *ptr, int v) +{ + return _cmpccxadd_epi32(ptr, v, 1, _CMPCCX_O) < v; +} + +_Bool foo_sete(int *ptr, int v) +{ + return _cmpccxadd_epi32(ptr, v, 1, _CMPCCX_O) == v; +} + +_Bool foo_setne(int *ptr, int v) +{ + return _cmpccxadd_epi32(ptr, v, 1, _CMPCCX_O) != v; +} + +_Bool foo_setge(int *ptr, int v) +{ + return _cmpccxadd_epi32(ptr, v, 1, _CMPCCX_O) >= v; +} + +_Bool foo_setle(int *ptr, int v) +{ + return _cmpccxadd_epi32(ptr, v, 1, _CMPCCX_O) <= v; +} + +_Bool fooq_setg (long long *ptr, long long v) +{ + return _cmpccxadd_epi64(ptr, v, 1, _CMPCCX_O) > v; +} + +_Bool fooq_setl (long long *ptr, long long v) +{ + return _cmpccxadd_epi64(ptr, v, 1, _CMPCCX_O) < v; +} + +_Bool fooq_sete(long long *ptr, long long v) +{ + return _cmpccxadd_epi64(ptr, v, 1, _CMPCCX_O) == v; +} + +_Bool fooq_setne(long long *ptr, long long v) +{ + return _cmpccxadd_epi64(ptr, v, 1, _CMPCCX_O) != v; +} + +_Bool fooq_setge(long long *ptr, long long v) +{ + return _cmpccxadd_epi64(ptr, v, 1, _CMPCCX_O) >= v; +} + +_Bool fooq_setle(long long *ptr, long long v) +{ + return _cmpccxadd_epi64(ptr, v, 1, _CMPCCX_O) <= v; +}