diff mbox series

[v2] RISC-V: fix expand function of vlmul_ext RVV intrinsic

Message ID 20230625090932.18330-1-xuli1@eswincomputing.com
State New
Headers show
Series [v2] RISC-V: fix expand function of vlmul_ext RVV intrinsic | expand

Commit Message

Li Xu June 25, 2023, 9:09 a.m. UTC 
Consider this following case:
void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
  vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
}

Compilation fails with:
test.c: In function 'test_vlmul_ext_v_i8mf8_i8mf4':
test.c:5:1: error: unrecognizable insn:
    5 | }
      | ^
(insn 30 29 0 2 (set (mem/c:VNx2QI (reg/f:DI 143) [0 x+0 S[2, 2] A32])
        (mem/c:VNx2QI (reg/f:DI 148) [0 op1+0 S[2, 2] A16])) "test.c":4:18 -1
     (nil))
during RTL pass: vregs
test.c:5:1: internal compiler error: in extract_insn, at recog.cc:2791
0x7c61b8 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*)
        ../.././riscv-gcc/gcc/rtl-error.cc:108
0x7c61d7 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        ../.././riscv-gcc/gcc/rtl-error.cc:116
0xed58a7 extract_insn(rtx_insn*)
        ../.././riscv-gcc/gcc/recog.cc:2791
0xb7f789 instantiate_virtual_regs_in_insn
        ../.././riscv-gcc/gcc/function.cc:1611
0xb7f789 instantiate_virtual_regs
        ../.././riscv-gcc/gcc/function.cc:1984

gcc/ChangeLog:

        * config/riscv/riscv-vector-builtins-bases.cc: change emit_insn to emit_move_insn

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vlmul_ext-2.c: New test.
---
 gcc/config/riscv/riscv-vector-builtins-bases.cc       | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c | 8 ++++++++
 2 files changed, 9 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c

Comments

Juzhe-Zhong June 25, 2023, 9:13 a.m. UTC | #1 
LGTM.
Thanks for fixing it.

Hi, Jeff:
I saw Li Xu is frequently helping RVV support in GCC. Is it possible to give him the write access?

Thanks.


juzhe.zhong@rivai.ai
 
From: Li Xu
Date: 2023-06-25 17:09
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; zhengyu; Li Xu
Subject: [PATCH v2] RISC-V: fix expand function of vlmul_ext RVV intrinsic
Consider this following case:
void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
  vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
}
 
Compilation fails with:
test.c: In function 'test_vlmul_ext_v_i8mf8_i8mf4':
test.c:5:1: error: unrecognizable insn:
    5 | }
      | ^
(insn 30 29 0 2 (set (mem/c:VNx2QI (reg/f:DI 143) [0 x+0 S[2, 2] A32])
        (mem/c:VNx2QI (reg/f:DI 148) [0 op1+0 S[2, 2] A16])) "test.c":4:18 -1
     (nil))
during RTL pass: vregs
test.c:5:1: internal compiler error: in extract_insn, at recog.cc:2791
0x7c61b8 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*)
        ../.././riscv-gcc/gcc/rtl-error.cc:108
0x7c61d7 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        ../.././riscv-gcc/gcc/rtl-error.cc:116
0xed58a7 extract_insn(rtx_insn*)
        ../.././riscv-gcc/gcc/recog.cc:2791
0xb7f789 instantiate_virtual_regs_in_insn
        ../.././riscv-gcc/gcc/function.cc:1611
0xb7f789 instantiate_virtual_regs
        ../.././riscv-gcc/gcc/function.cc:1984
 
gcc/ChangeLog:
 
        * config/riscv/riscv-vector-builtins-bases.cc: change emit_insn to emit_move_insn
 
gcc/testsuite/ChangeLog:
 
        * gcc.target/riscv/rvv/base/vlmul_ext-2.c: New test.
---
gcc/config/riscv/riscv-vector-builtins-bases.cc       | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c | 8 ++++++++
2 files changed, 9 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
 
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index c6c53dc13a5..5c8deda900d 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1567,7 +1567,7 @@ public:
   {
     tree arg = CALL_EXPR_ARG (e.exp, 0);
     rtx src = expand_normal (arg);
-    emit_insn (gen_rtx_SET (gen_lowpart (e.vector_mode (), e.target), src));
+    emit_move_insn (gen_lowpart (e.vector_mode (), e.target), src);
     return e.target;
   }
};
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
new file mode 100644
index 00000000000..2b088b53546
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
+
+#include "riscv_vector.h"
+
+void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
+  vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
+}
Jeff Law June 25, 2023, 12:54 p.m. UTC | #2 
On 6/25/23 03:13, juzhe.zhong@rivai.ai wrote:
> LGTM.
> Thanks for fixing it.
Agreed.  I didn't see the V2 had already been posted.

> 
> Hi, Jeff:
> I saw Li Xu is frequently helping RVV support in GCC. Is it possible to 
> give him the write access?
Yes, we can do that with the normal process.

Li Xu, fill out this form:

https://sourceware.org/cgi-bin/pdw/ps_form.cgi

List me as approving the request.
Jeff
Li, Pan2 via Gcc-patches June 25, 2023, 2:06 p.m. UTC | #3 
Committed, thanks Jeff.

Pan

-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Jeff Law via Gcc-patches
Sent: Sunday, June 25, 2023 8:55 PM
To: juzhe.zhong@rivai.ai; Li Xu <xuli1@eswincomputing.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; palmer <palmer@dabbelt.com>; zhengyu <zhengyu@eswincomputing.com>
Subject: Re: [PATCH v2] RISC-V: fix expand function of vlmul_ext RVV intrinsic



On 6/25/23 03:13, juzhe.zhong@rivai.ai wrote:
> LGTM.
> Thanks for fixing it.
Agreed.  I didn't see the V2 had already been posted.

> 
> Hi, Jeff:
> I saw Li Xu is frequently helping RVV support in GCC. Is it possible to 
> give him the write access?
Yes, we can do that with the normal process.

Li Xu, fill out this form:

https://sourceware.org/cgi-bin/pdw/ps_form.cgi

List me as approving the request.
Jeff
Li Xu June 26, 2023, 9:16 a.m. UTC | #4 
Hi, Jeff:

I have filled out the form. May I ask if you have received my application? Is there anything else I need to do?

Thanks.
--------------
Li Xu
>
>
>On 6/25/23 03:13, juzhe.zhong@rivai.ai wrote:
>> LGTM.
>> Thanks for fixing it.
>Agreed.  I didn't see the V2 had already been posted.
>
>>
>> Hi, Jeff:
>> I saw Li Xu is frequently helping RVV support in GCC. Is it possible to
>> give him the write access?
>Yes, we can do that with the normal process.
>
>Li Xu, fill out this form:
>
>https://sourceware.org/cgi-bin/pdw/ps_form.cgi
>
>List me as approving the request.
>Jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index c6c53dc13a5..5c8deda900d 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1567,7 +1567,7 @@  public:
   {
     tree arg = CALL_EXPR_ARG (e.exp, 0);
     rtx src = expand_normal (arg);
-    emit_insn (gen_rtx_SET (gen_lowpart (e.vector_mode (), e.target), src));
+    emit_move_insn (gen_lowpart (e.vector_mode (), e.target), src);
     return e.target;
   }
 };
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
new file mode 100644
index 00000000000..2b088b53546
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
@@ -0,0 +1,8 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
+
+#include "riscv_vector.h"
+
+void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
+  vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
+}