new file mode 100644
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+
+#include <stdint-gcc.h>
+
+#define VEC_PERM(TYPE) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ vec_slp_##TYPE (TYPE *restrict a, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ a[i * 2] += 10; \
+ a[i * 2 + 1] += 17; \
+ } \
+ }
+
+#define TEST_ALL(T) \
+ T (int8_t) \
+ T (uint8_t) \
+ T (int16_t) \
+ T (uint16_t) \
+ T (int32_t) \
+ T (uint32_t) \
+ T (int64_t) \
+ T (uint64_t)
+
+TEST_ALL (VEC_PERM)
+
+/* { dg-final { scan-tree-dump-times "{ 10, 17, ... }" 8 "optimized" } } */
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
+
new file mode 100644
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+
+#include <stdint-gcc.h>
+
+#define VEC_PERM(TYPE) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ vec_slp_##TYPE (TYPE *restrict a, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ a[i * 4] += 41; \
+ a[i * 4 + 1] += 25; \
+ a[i * 4 + 2] += 31; \
+ a[i * 4 + 3] += 62; \
+ } \
+ }
+
+#define TEST_ALL(T) \
+ T (int8_t) \
+ T (uint8_t) \
+ T (int16_t) \
+ T (uint16_t) \
+ T (int32_t) \
+ T (uint32_t) \
+ T (int64_t) \
+ T (uint64_t)
+
+TEST_ALL (VEC_PERM)
+
+/* { dg-final { scan-tree-dump "{ 41, 25, 31, 62, ... }" "optimized" } } */
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
new file mode 100644
@@ -0,0 +1,33 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "slp-10.c"
+
+#define N (103 * 2)
+
+#define HARNESS(TYPE) \
+ { \
+ TYPE a[N], b[2] = { 10, 17 }; \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ a[i] = i * 2 + i % 5; \
+ asm volatile ("" ::: "memory"); \
+ } \
+ vec_slp_##TYPE (a, N / 2); \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ TYPE orig = i * 2 + i % 5; \
+ TYPE expected = orig + b[i % 2]; \
+ if (a[i] != expected) \
+ __builtin_abort (); \
+ } \
+ }
+
+int __attribute__ ((optimize (1)))
+main (void)
+{
+ TEST_ALL (HARNESS)
+}
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
new file mode 100644
@@ -0,0 +1,33 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "slp-11.c"
+
+#define N (77 * 4)
+
+#define HARNESS(TYPE) \
+ { \
+ TYPE a[N], b[4] = { 41, 25, 31, 62 }; \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ a[i] = i * 2 + i % 5; \
+ asm volatile ("" ::: "memory"); \
+ } \
+ vec_slp_##TYPE (a, N / 4); \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ TYPE orig = i * 2 + i % 5; \
+ TYPE expected = orig + b[i % 4]; \
+ if (a[i] != expected) \
+ __builtin_abort (); \
+ } \
+ }
+
+int __attribute__ ((optimize (1)))
+main (void)
+{
+ TEST_ALL (HARNESS)
+}
+
+/* This testcase is from aarch64 and floating-point operations are removed.
+ TODO: We will add floating-point operations back and make them as common test in the future. */
From: Juzhe-Zhong <juzhe.zhong@rivai.ai> gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/slp-10.c: New test. * gcc.target/riscv/rvv/autovec/partial/slp-11.c: New test. * gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: New test. * gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: New test. --- .../riscv/rvv/autovec/partial/slp-10.c | 32 ++++++++++++++++++ .../riscv/rvv/autovec/partial/slp-11.c | 33 +++++++++++++++++++ .../riscv/rvv/autovec/partial/slp_run-10.c | 33 +++++++++++++++++++ .../riscv/rvv/autovec/partial/slp_run-11.c | 33 +++++++++++++++++++ 4 files changed, 131 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c