| Message ID | 20230531102327.199390-1-juzhe.zhong@rivai.ai |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Add testcase for vrsub.vi auto-vectorization | expand |
On 5/31/23 04:23, juzhe.zhong@rivai.ai wrote: > From: Juzhe-Zhong <juzhe.zhong@rivai.ai> > > Apparently, we are missing vrsub.vi tests. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Add vsub.vi. > * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto. > * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto. > * gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Ditto. OK jeff
Committed, thanks Jeff. Pan -----Original Message----- From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Jeff Law via Gcc-patches Sent: Wednesday, May 31, 2023 9:07 PM To: juzhe.zhong@rivai.ai; gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com; kito.cheng@sifive.com; palmer@dabbelt.com; palmer@rivosinc.com; rdapp.gcc@gmail.com Subject: Re: [PATCH] RISC-V: Add testcase for vrsub.vi auto-vectorization On 5/31/23 04:23, juzhe.zhong@rivai.ai wrote: > From: Juzhe-Zhong <juzhe.zhong@rivai.ai> > > Apparently, we are missing vrsub.vi tests. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Add vsub.vi. > * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto. > * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto. > * gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Ditto. OK jeff
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c index 8c6d8e88d1a..4f254872e33 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c @@ -27,6 +27,22 @@ for (int i = 0; i < SZ; i++) \ assert (as##TYPE[i] == 999 - VAL); +#define RUN3(TYPE) \ + TYPE as2##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + as2##TYPE[i] = i * 33 - 779; \ + vsubi_##TYPE (as2##TYPE, as2##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (as2##TYPE[i] == (TYPE)(-16 - (i * 33 - 779))); + +#define RUN4(TYPE) \ + TYPE as3##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + as3##TYPE[i] = i * -17 + 667; \ + vsubi2_##TYPE (as3##TYPE, as3##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (as3##TYPE[i] == (TYPE)(15 - (i * -17 + 667))); + #define RUN_ALL() \ RUN(int16_t, 1) \ RUN(uint16_t, 2) \ @@ -39,7 +55,19 @@ RUN2(int32_t, 9) \ RUN2(uint32_t, 10) \ RUN2(int64_t, 11) \ - RUN2(uint64_t, 12) + RUN2(uint64_t, 12) \ + RUN3(int16_t) \ + RUN3(uint16_t) \ + RUN3(int32_t) \ + RUN3(uint32_t) \ + RUN3(int64_t) \ + RUN3(uint64_t) \ + RUN4(int16_t) \ + RUN4(uint16_t) \ + RUN4(int32_t) \ + RUN4(uint32_t) \ + RUN4(int64_t) \ + RUN4(uint64_t) int main () { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c index e2bdd0fe904..a0d3802be65 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c @@ -4,3 +4,4 @@ #include "vsub-template.h" /* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */ +/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c index f7a2691b9f3..562c026a7e4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c @@ -4,3 +4,4 @@ #include "vsub-template.h" /* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */ +/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h index 8c0a9c99217..47f07f13462 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h @@ -16,6 +16,22 @@ dst[i] = a[i] - b; \ } +#define TEST3_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vsubi_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = -16 - a[i]; \ + } + +#define TEST4_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vsubi2_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = 15 - a[i]; \ + } + /* *int8_t not autovec currently. */ #define TEST_ALL() \ TEST_TYPE(int16_t) \ @@ -30,5 +46,17 @@ TEST2_TYPE(uint32_t) \ TEST2_TYPE(int64_t) \ TEST2_TYPE(uint64_t) + TEST3_TYPE(int16_t) \ + TEST3_TYPE(uint16_t) \ + TEST3_TYPE(int32_t) \ + TEST3_TYPE(uint32_t) \ + TEST3_TYPE(int64_t) \ + TEST3_TYPE(uint64_t) \ + TEST4_TYPE(int16_t) \ + TEST4_TYPE(uint16_t) \ + TEST4_TYPE(int32_t) \ + TEST4_TYPE(uint32_t) \ + TEST4_TYPE(int64_t) \ + TEST4_TYPE(uint64_t) TEST_ALL()
From: Juzhe-Zhong <juzhe.zhong@rivai.ai> Apparently, we are missing vrsub.vi tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Add vsub.vi. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Ditto. --- .../riscv/rvv/autovec/binop/vsub-run.c | 30 ++++++++++++++++++- .../riscv/rvv/autovec/binop/vsub-rv32gcv.c | 1 + .../riscv/rvv/autovec/binop/vsub-rv64gcv.c | 1 + .../riscv/rvv/autovec/binop/vsub-template.h | 28 +++++++++++++++++ 4 files changed, 59 insertions(+), 1 deletion(-)