| Message ID | 20230418070450.4114708-2-haochen.jiang@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | i386: Add missing AVX512BW dependency for ISAs using 32/64 bit mask | expand |
On Tue, Apr 18, 2023 at 3:07 PM Haochen Jiang via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > gcc/ChangeLog: > > * common/config/i386/i386-common.cc > (OPTION_MASK_ISA_AVX512BITALG_SET): > Change OPTION_MASK_ISA_AVX512F_SET > to OPTION_MASK_ISA_AVX512BW_SET. > (OPTION_MASK_ISA_AVX512F_UNSET): > Remove OPTION_MASK_ISA_AVX512BITALG_SET. > (OPTION_MASK_ISA_AVX512BW_UNSET): > Add OPTION_MASK_ISA_AVX512BITALG_SET. > * config/i386/avx512bitalgintrin.h: Do not push avx512bw. > * config/i386/i386-builtin.def: > Remove redundant OPTION_MASK_ISA_AVX512BW. > * config/i386/sse.md (VI1_AVX512VLBW): Removed. > (avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>): > Change the iterator from VI1_AVX512VLBW to VI1_AVX512VL. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/avx512bitalg-vpopcntb-1.c: > Remove avx512bw. > * gcc.target/i386/avx512bitalg-vpopcntb.c: Ditto. > * gcc.target/i386/avx512bitalg-vpopcntbvl.c: Ditto. > * gcc.target/i386/avx512bitalg-vpopcntw-1.c: Ditto. > * gcc.target/i386/avx512bitalg-vpopcntw.c: Ditto. > * gcc.target/i386/avx512bitalg-vpopcntwvl.c: Ditto. > * gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c: Ditto. > * gcc.target/i386/avx512bitalg-vpshufbitqmb.c: Ditto. > * gcc.target/i386/avx512bitalgvl-vpopcntb-1.c: Ditto. > * gcc.target/i386/avx512bitalgvl-vpopcntw-1.c: Ditto. > * gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c: Ditto. > * gcc.target/i386/pr93696-1.c: Ditto. > * gcc.target/i386/pr93696-2.c: Ditto. Ok. > --- > gcc/common/config/i386/i386-common.cc | 8 ++-- > gcc/config/i386/avx512bitalgintrin.h | 39 ++++--------------- > gcc/config/i386/i386-builtin.def | 10 ++--- > gcc/config/i386/sse.md | 8 +--- > .../gcc.target/i386/avx512bitalg-vpopcntb-1.c | 3 +- > .../gcc.target/i386/avx512bitalg-vpopcntb.c | 2 +- > .../gcc.target/i386/avx512bitalg-vpopcntbvl.c | 2 +- > .../gcc.target/i386/avx512bitalg-vpopcntw-1.c | 3 +- > .../gcc.target/i386/avx512bitalg-vpopcntw.c | 2 +- > .../gcc.target/i386/avx512bitalg-vpopcntwvl.c | 2 +- > .../i386/avx512bitalg-vpshufbitqmb-1.c | 2 +- > .../i386/avx512bitalg-vpshufbitqmb.c | 2 +- > .../i386/avx512bitalgvl-vpopcntb-1.c | 3 +- > .../i386/avx512bitalgvl-vpopcntw-1.c | 3 +- > .../i386/avx512bitalgvl-vpshufbitqmb-1.c | 2 +- > gcc/testsuite/gcc.target/i386/pr93696-1.c | 2 +- > gcc/testsuite/gcc.target/i386/pr93696-2.c | 2 +- > 17 files changed, 32 insertions(+), 63 deletions(-) > > diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc > index d90c558311b..f78fc0a60e2 100644 > --- a/gcc/common/config/i386/i386-common.cc > +++ b/gcc/common/config/i386/i386-common.cc > @@ -91,7 +91,7 @@ along with GCC; see the file COPYING3. If not see > #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \ > (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET) > #define OPTION_MASK_ISA_AVX512BITALG_SET \ > - (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET) > + (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW_SET) > #define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16 > #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM > #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW > @@ -234,14 +234,14 @@ along with GCC; see the file COPYING3. If not see > | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \ > | OPTION_MASK_ISA_AVX512VBMI2_UNSET \ > | OPTION_MASK_ISA_AVX512VNNI_UNSET \ > - | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \ > - | OPTION_MASK_ISA_AVX512BITALG_UNSET) > + | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET) > #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD > #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF > #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER > #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ > #define OPTION_MASK_ISA_AVX512BW_UNSET \ > - (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET) > + (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET \ > + | OPTION_MASK_ISA_AVX512BITALG_UNSET) > #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL > #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA > #define OPTION_MASK_ISA2_AVXIFMA_UNSET OPTION_MASK_ISA2_AVXIFMA > diff --git a/gcc/config/i386/avx512bitalgintrin.h b/gcc/config/i386/avx512bitalgintrin.h > index aa6d652938a..a1c7be109a9 100644 > --- a/gcc/config/i386/avx512bitalgintrin.h > +++ b/gcc/config/i386/avx512bitalgintrin.h > @@ -48,17 +48,6 @@ _mm512_popcnt_epi16 (__m512i __A) > return (__m512i) __builtin_ia32_vpopcountw_v32hi ((__v32hi) __A); > } > > -#ifdef __DISABLE_AVX512BITALG__ > -#undef __DISABLE_AVX512BITALG__ > -#pragma GCC pop_options > -#endif /* __DISABLE_AVX512BITALG__ */ > - > -#if !defined(__AVX512BITALG__) || !defined(__AVX512BW__) > -#pragma GCC push_options > -#pragma GCC target("avx512bitalg,avx512bw") > -#define __DISABLE_AVX512BITALGBW__ > -#endif /* __AVX512VLBW__ */ > - > extern __inline __m512i > __attribute__((__gnu_inline__, __always_inline__, __artificial__)) > _mm512_mask_popcnt_epi8 (__m512i __W, __mmask64 __U, __m512i __A) > @@ -114,16 +103,16 @@ _mm512_mask_bitshuffle_epi64_mask (__mmask64 __M, __m512i __A, __m512i __B) > (__mmask64) __M); > } > > -#ifdef __DISABLE_AVX512BITALGBW__ > -#undef __DISABLE_AVX512BITALGBW__ > +#ifdef __DISABLE_AVX512BITALG__ > +#undef __DISABLE_AVX512BITALG__ > #pragma GCC pop_options > -#endif /* __DISABLE_AVX512BITALGBW__ */ > +#endif /* __DISABLE_AVX512BITALG__ */ > > -#if !defined(__AVX512BITALG__) || !defined(__AVX512VL__) || !defined(__AVX512BW__) > +#if !defined(__AVX512BITALG__) || !defined(__AVX512VL__) > #pragma GCC push_options > -#pragma GCC target("avx512bitalg,avx512vl,avx512bw") > -#define __DISABLE_AVX512BITALGVLBW__ > -#endif /* __AVX512VLBW__ */ > +#pragma GCC target("avx512bitalg,avx512vl") > +#define __DISABLE_AVX512BITALGVL__ > +#endif /* __AVX512BITALGVL__ */ > > extern __inline __m256i > __attribute__((__gnu_inline__, __always_inline__, __artificial__)) > @@ -162,18 +151,6 @@ _mm256_mask_bitshuffle_epi64_mask (__mmask32 __M, __m256i __A, __m256i __B) > (__mmask32) __M); > } > > -#ifdef __DISABLE_AVX512BITALGVLBW__ > -#undef __DISABLE_AVX512BITALGVLBW__ > -#pragma GCC pop_options > -#endif /* __DISABLE_AVX512BITALGVLBW__ */ > - > - > -#if !defined(__AVX512BITALG__) || !defined(__AVX512VL__) > -#pragma GCC push_options > -#pragma GCC target("avx512bitalg,avx512vl") > -#define __DISABLE_AVX512BITALGVL__ > -#endif /* __AVX512VLBW__ */ > - > extern __inline __mmask16 > __attribute__((__gnu_inline__, __always_inline__, __artificial__)) > _mm_bitshuffle_epi64_mask (__m128i __A, __m128i __B) > @@ -278,6 +255,6 @@ _mm_maskz_popcnt_epi16 (__mmask8 __U, __m128i __A) > #ifdef __DISABLE_AVX512BITALGVL__ > #undef __DISABLE_AVX512BITALGVL__ > #pragma GCC pop_options > -#endif /* __DISABLE_AVX512BITALGBW__ */ > +#endif /* __DISABLE_AVX512BITALGVL__ */ > > #endif /* _AVX512BITALGINTRIN_H_INCLUDED */ > diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def > index 6dae6972d81..c4167307992 100644 > --- a/gcc/config/i386/i386-builtin.def > +++ b/gcc/config/i386/i386-builtin.def > @@ -2762,21 +2762,21 @@ BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_v > > /* BITALG */ > BDESC (OPTION_MASK_ISA_AVX512BITALG, 0, CODE_FOR_vpopcountv64qi, "__builtin_ia32_vpopcountb_v64qi", IX86_BUILTIN_VPOPCOUNTBV64QI, UNKNOWN, (int) V64QI_FTYPE_V64QI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW, 0, CODE_FOR_vpopcountv64qi_mask, "__builtin_ia32_vpopcountb_v64qi_mask", IX86_BUILTIN_VPOPCOUNTBV64QI_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG, 0, CODE_FOR_vpopcountv64qi_mask, "__builtin_ia32_vpopcountb_v64qi_mask", IX86_BUILTIN_VPOPCOUNTBV64QI_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI) > BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv32qi, "__builtin_ia32_vpopcountb_v32qi", IX86_BUILTIN_VPOPCOUNTBV32QI, UNKNOWN, (int) V32QI_FTYPE_V32QI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW, 0, CODE_FOR_vpopcountv32qi_mask, "__builtin_ia32_vpopcountb_v32qi_mask", IX86_BUILTIN_VPOPCOUNTBV32QI_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv32qi_mask, "__builtin_ia32_vpopcountb_v32qi_mask", IX86_BUILTIN_VPOPCOUNTBV32QI_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI) > BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv16qi, "__builtin_ia32_vpopcountb_v16qi", IX86_BUILTIN_VPOPCOUNTBV16QI, UNKNOWN, (int) V16QI_FTYPE_V16QI) > BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv16qi_mask, "__builtin_ia32_vpopcountb_v16qi_mask", IX86_BUILTIN_VPOPCOUNTBV16QI_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI) > > BDESC (OPTION_MASK_ISA_AVX512BITALG, 0, CODE_FOR_vpopcountv32hi, "__builtin_ia32_vpopcountw_v32hi", IX86_BUILTIN_VPOPCOUNTWV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW, 0, CODE_FOR_vpopcountv32hi_mask, "__builtin_ia32_vpopcountw_v32hi_mask", IX86_BUILTIN_VPOPCOUNTQV32HI_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_USI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG, 0, CODE_FOR_vpopcountv32hi_mask, "__builtin_ia32_vpopcountw_v32hi_mask", IX86_BUILTIN_VPOPCOUNTQV32HI_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_USI) > BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv16hi, "__builtin_ia32_vpopcountw_v16hi", IX86_BUILTIN_VPOPCOUNTWV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI) > BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv16hi_mask, "__builtin_ia32_vpopcountw_v16hi_mask", IX86_BUILTIN_VPOPCOUNTQV16HI_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_UHI) > BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv8hi, "__builtin_ia32_vpopcountw_v8hi", IX86_BUILTIN_VPOPCOUNTWV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI) > BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv8hi_mask, "__builtin_ia32_vpopcountw_v8hi_mask", IX86_BUILTIN_VPOPCOUNTQV8HI_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_UQI) > > -BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW, 0, CODE_FOR_avx512vl_vpshufbitqmbv64qi_mask, "__builtin_ia32_vpshufbitqmb512_mask", IX86_BUILTIN_VPSHUFBITQMB512_MASK, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_UDI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW, 0, CODE_FOR_avx512vl_vpshufbitqmbv32qi_mask, "__builtin_ia32_vpshufbitqmb256_mask", IX86_BUILTIN_VPSHUFBITQMB256_MASK, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_USI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG, 0, CODE_FOR_avx512vl_vpshufbitqmbv64qi_mask, "__builtin_ia32_vpshufbitqmb512_mask", IX86_BUILTIN_VPSHUFBITQMB512_MASK, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_UDI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_vpshufbitqmbv32qi_mask, "__builtin_ia32_vpshufbitqmb256_mask", IX86_BUILTIN_VPSHUFBITQMB256_MASK, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_USI) > BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_vpshufbitqmbv16qi_mask, "__builtin_ia32_vpshufbitqmb128_mask", IX86_BUILTIN_VPSHUFBITQMB128_MASK, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_UHI) > > /* AVX512_4FMAPS and AVX512_4VNNIW builtins with variable number of arguments. Defined in additional ix86_isa_flags2. */ > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 5b6b2427460..deb2d747ec1 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -686,10 +686,6 @@ > (define_mode_iterator VF4_128_8_256 > [V4DF V4SF]) > > -(define_mode_iterator VI1_AVX512VLBW > - [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX512VL") > - (V16QI "TARGET_AVX512VL")]) > - > (define_mode_attr avx512 > [(V16QI "avx512vl") (V32QI "avx512vl") (V64QI "avx512bw") > (V8HI "avx512vl") (V16HI "avx512vl") (V32HI "avx512bw") > @@ -28853,8 +28849,8 @@ > (define_insn "avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>" > [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k") > (unspec:<avx512fmaskmode> > - [(match_operand:VI1_AVX512VLBW 1 "register_operand" "v") > - (match_operand:VI1_AVX512VLBW 2 "nonimmediate_operand" "vm")] > + [(match_operand:VI1_AVX512VL 1 "register_operand" "v") > + (match_operand:VI1_AVX512VL 2 "nonimmediate_operand" "vm")] > UNSPEC_VPSHUFBIT))] > "TARGET_AVX512BITALG" > "vpshufbitqmb\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}" > diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb-1.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb-1.c > index 697757b8b73..93afe13227f 100644 > --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb-1.c > +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb-1.c > @@ -1,7 +1,6 @@ > /* { dg-do run } */ > -/* { dg-options "-O2 -mavx512bitalg -mavx512bw" } */ > +/* { dg-options "-O2 -mavx512bitalg" } */ > /* { dg-require-effective-target avx512bitalg } */ > -/* { dg-require-effective-target avx512bw } */ > > #define AVX512BITALG > #define SIZE (AVX512F_LEN / 8) > diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb.c > index 246f925eede..44b82c0519d 100644 > --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb.c > +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O2 -mavx512bitalg -mavx512bw" } */ > +/* { dg-options "-O2 -mavx512bitalg" } */ > /* { dg-final { scan-assembler-times "vpopcntb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > /* { dg-final { scan-assembler-times "vpopcntb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > /* { dg-final { scan-assembler-times "vpopcntb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntbvl.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntbvl.c > index 8c7f45fc5f7..8c2dfaba9c6 100644 > --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntbvl.c > +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntbvl.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O2 -mavx512bitalg -mavx512bw -mavx512vl" } */ > +/* { dg-options "-O2 -mavx512bitalg -mavx512vl" } */ > /* { dg-final { scan-assembler-times "vpopcntb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > /* { dg-final { scan-assembler-times "vpopcntb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > /* { dg-final { scan-assembler-times "vpopcntb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw-1.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw-1.c > index 0a725fe012a..93e2be23f1f 100644 > --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw-1.c > +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw-1.c > @@ -1,7 +1,6 @@ > /* { dg-do run } */ > -/* { dg-options "-O2 -mavx512bitalg -mavx512bw" } */ > +/* { dg-options "-O2 -mavx512bitalg" } */ > /* { dg-require-effective-target avx512bitalg } */ > -/* { dg-require-effective-target avx512bw } */ > > #define AVX512BITALG > #define SIZE (AVX512F_LEN / 16) > diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw.c > index 90663f480fc..2ef8589f6c1 100644 > --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw.c > +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O2 -mavx512bitalg -mavx512bw" } */ > +/* { dg-options "-O2 -mavx512bitalg" } */ > /* { dg-final { scan-assembler-times "vpopcntw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > /* { dg-final { scan-assembler-times "vpopcntw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > /* { dg-final { scan-assembler-times "vpopcntw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntwvl.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntwvl.c > index 3a646b57282..c976461b12e 100644 > --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntwvl.c > +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntwvl.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O2 -mavx512bitalg -mavx512bw -mavx512vl" } */ > +/* { dg-options "-O2 -mavx512bitalg -mavx512vl" } */ > /* { dg-final { scan-assembler-times "vpopcntw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > /* { dg-final { scan-assembler-times "vpopcntw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > /* { dg-final { scan-assembler-times "vpopcntw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c > index 668064aa4e1..5e881484bde 100644 > --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c > +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c > @@ -1,5 +1,5 @@ > /* { dg-do run } */ > -/* { dg-options "-O2 -mavx512bitalg -mavx512f -mavx512bw" } */ > +/* { dg-options "-O2 -mavx512bitalg" } */ > /* { dg-require-effective-target avx512bitalg } */ > > #define AVX512BITALG > diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb.c > index 7acb0c203f3..75fbef89732 100644 > --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb.c > +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-mavx512bitalg -mavx512vl -mavx512bw -O2" } */ > +/* { dg-options "-mavx512bitalg -mavx512vl -O2" } */ > /* { dg-final { scan-assembler-times "vpshufbitqmb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > /* { dg-final { scan-assembler-times "vpshufbitqmb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > /* { dg-final { scan-assembler-times "vpshufbitqmb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntb-1.c b/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntb-1.c > index 607ec3ff3df..a4e9d63fc1c 100644 > --- a/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntb-1.c > +++ b/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntb-1.c > @@ -1,8 +1,7 @@ > /* { dg-do run } */ > -/* { dg-options "-O2 -mavx512vl -mavx512bitalg -mavx512bw" } */ > +/* { dg-options "-O2 -mavx512vl -mavx512bitalg" } */ > /* { dg-require-effective-target avx512vl } */ > /* { dg-require-effective-target avx512bitalg } */ > -/* { dg-require-effective-target avx512bw } */ > > #define AVX512VL > #define AVX512F_LEN 256 > diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntw-1.c b/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntw-1.c > index 3d7e2b5eb11..55fa811fb46 100644 > --- a/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntw-1.c > +++ b/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntw-1.c > @@ -1,8 +1,7 @@ > /* { dg-do run } */ > -/* { dg-options "-O2 -mavx512vl -mavx512bitalg -mavx512bw" } */ > +/* { dg-options "-O2 -mavx512vl -mavx512bitalg" } */ > /* { dg-require-effective-target avx512vl } */ > /* { dg-require-effective-target avx512bitalg } */ > -/* { dg-require-effective-target avx512bw } */ > > #define AVX512VL > #define AVX512F_LEN 256 > diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c b/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c > index 76598c44946..497e369bf80 100644 > --- a/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c > +++ b/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c > @@ -1,5 +1,5 @@ > /* { dg-do run } */ > -/* { dg-options "-O2 -mavx512vl -mavx512bitalg -mavx512bw" } */ > +/* { dg-options "-O2 -mavx512vl -mavx512bitalg" } */ > /* { dg-require-effective-target avx512vl } */ > /* { dg-require-effective-target avx512bitalg } */ > > diff --git a/gcc/testsuite/gcc.target/i386/pr93696-1.c b/gcc/testsuite/gcc.target/i386/pr93696-1.c > index 128bb98c066..70f0f8ad8e1 100644 > --- a/gcc/testsuite/gcc.target/i386/pr93696-1.c > +++ b/gcc/testsuite/gcc.target/i386/pr93696-1.c > @@ -1,6 +1,6 @@ > /* PR target/93696 */ > /* { dg-do compile } */ > -/* { dg-options "-O2 -mavx512bitalg -mavx512vpopcntdq -mavx512vl -mavx512bw -masm=att" } */ > +/* { dg-options "-O2 -mavx512bitalg -mavx512vpopcntdq -mavx512vl -masm=att" } */ > /* { dg-final { scan-assembler-times "vpopcnt\[bwdq]\t%\[xyz]mm1, %\[xyz]mm0\{%k\[0-7]\}\[^\{]" 12 } } */ > /* { dg-final { scan-assembler-not "vmovdq\[au]\[0-9]" } } */ > > diff --git a/gcc/testsuite/gcc.target/i386/pr93696-2.c b/gcc/testsuite/gcc.target/i386/pr93696-2.c > index 25a298aea18..e6aabd4d081 100644 > --- a/gcc/testsuite/gcc.target/i386/pr93696-2.c > +++ b/gcc/testsuite/gcc.target/i386/pr93696-2.c > @@ -1,6 +1,6 @@ > /* PR target/93696 */ > /* { dg-do compile } */ > -/* { dg-options "-O2 -mavx512bitalg -mavx512vpopcntdq -mavx512vl -mavx512bw -masm=att" } */ > +/* { dg-options "-O2 -mavx512bitalg -mavx512vpopcntdq -mavx512vl -masm=att" } */ > /* { dg-final { scan-assembler-times "vpopcnt\[bwdq]\t%\[xyz]mm1, %\[xyz]mm0\{%k\[0-7]\}\{z\}" 12 } } */ > /* { dg-final { scan-assembler-not "vmovdq\[au]\[0-9]" } } */ > > -- > 2.31.1 >
diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index d90c558311b..f78fc0a60e2 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -91,7 +91,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \ (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET) #define OPTION_MASK_ISA_AVX512BITALG_SET \ - (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET) + (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW_SET) #define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW @@ -234,14 +234,14 @@ along with GCC; see the file COPYING3. If not see | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \ | OPTION_MASK_ISA_AVX512VBMI2_UNSET \ | OPTION_MASK_ISA_AVX512VNNI_UNSET \ - | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \ - | OPTION_MASK_ISA_AVX512BITALG_UNSET) + | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET) #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ #define OPTION_MASK_ISA_AVX512BW_UNSET \ - (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET) + (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET \ + | OPTION_MASK_ISA_AVX512BITALG_UNSET) #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA #define OPTION_MASK_ISA2_AVXIFMA_UNSET OPTION_MASK_ISA2_AVXIFMA diff --git a/gcc/config/i386/avx512bitalgintrin.h b/gcc/config/i386/avx512bitalgintrin.h index aa6d652938a..a1c7be109a9 100644 --- a/gcc/config/i386/avx512bitalgintrin.h +++ b/gcc/config/i386/avx512bitalgintrin.h @@ -48,17 +48,6 @@ _mm512_popcnt_epi16 (__m512i __A) return (__m512i) __builtin_ia32_vpopcountw_v32hi ((__v32hi) __A); } -#ifdef __DISABLE_AVX512BITALG__ -#undef __DISABLE_AVX512BITALG__ -#pragma GCC pop_options -#endif /* __DISABLE_AVX512BITALG__ */ - -#if !defined(__AVX512BITALG__) || !defined(__AVX512BW__) -#pragma GCC push_options -#pragma GCC target("avx512bitalg,avx512bw") -#define __DISABLE_AVX512BITALGBW__ -#endif /* __AVX512VLBW__ */ - extern __inline __m512i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm512_mask_popcnt_epi8 (__m512i __W, __mmask64 __U, __m512i __A) @@ -114,16 +103,16 @@ _mm512_mask_bitshuffle_epi64_mask (__mmask64 __M, __m512i __A, __m512i __B) (__mmask64) __M); } -#ifdef __DISABLE_AVX512BITALGBW__ -#undef __DISABLE_AVX512BITALGBW__ +#ifdef __DISABLE_AVX512BITALG__ +#undef __DISABLE_AVX512BITALG__ #pragma GCC pop_options -#endif /* __DISABLE_AVX512BITALGBW__ */ +#endif /* __DISABLE_AVX512BITALG__ */ -#if !defined(__AVX512BITALG__) || !defined(__AVX512VL__) || !defined(__AVX512BW__) +#if !defined(__AVX512BITALG__) || !defined(__AVX512VL__) #pragma GCC push_options -#pragma GCC target("avx512bitalg,avx512vl,avx512bw") -#define __DISABLE_AVX512BITALGVLBW__ -#endif /* __AVX512VLBW__ */ +#pragma GCC target("avx512bitalg,avx512vl") +#define __DISABLE_AVX512BITALGVL__ +#endif /* __AVX512BITALGVL__ */ extern __inline __m256i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -162,18 +151,6 @@ _mm256_mask_bitshuffle_epi64_mask (__mmask32 __M, __m256i __A, __m256i __B) (__mmask32) __M); } -#ifdef __DISABLE_AVX512BITALGVLBW__ -#undef __DISABLE_AVX512BITALGVLBW__ -#pragma GCC pop_options -#endif /* __DISABLE_AVX512BITALGVLBW__ */ - - -#if !defined(__AVX512BITALG__) || !defined(__AVX512VL__) -#pragma GCC push_options -#pragma GCC target("avx512bitalg,avx512vl") -#define __DISABLE_AVX512BITALGVL__ -#endif /* __AVX512VLBW__ */ - extern __inline __mmask16 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_bitshuffle_epi64_mask (__m128i __A, __m128i __B) @@ -278,6 +255,6 @@ _mm_maskz_popcnt_epi16 (__mmask8 __U, __m128i __A) #ifdef __DISABLE_AVX512BITALGVL__ #undef __DISABLE_AVX512BITALGVL__ #pragma GCC pop_options -#endif /* __DISABLE_AVX512BITALGBW__ */ +#endif /* __DISABLE_AVX512BITALGVL__ */ #endif /* _AVX512BITALGINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 6dae6972d81..c4167307992 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2762,21 +2762,21 @@ BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_v /* BITALG */ BDESC (OPTION_MASK_ISA_AVX512BITALG, 0, CODE_FOR_vpopcountv64qi, "__builtin_ia32_vpopcountb_v64qi", IX86_BUILTIN_VPOPCOUNTBV64QI, UNKNOWN, (int) V64QI_FTYPE_V64QI) -BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW, 0, CODE_FOR_vpopcountv64qi_mask, "__builtin_ia32_vpopcountb_v64qi_mask", IX86_BUILTIN_VPOPCOUNTBV64QI_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI) +BDESC (OPTION_MASK_ISA_AVX512BITALG, 0, CODE_FOR_vpopcountv64qi_mask, "__builtin_ia32_vpopcountb_v64qi_mask", IX86_BUILTIN_VPOPCOUNTBV64QI_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI) BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv32qi, "__builtin_ia32_vpopcountb_v32qi", IX86_BUILTIN_VPOPCOUNTBV32QI, UNKNOWN, (int) V32QI_FTYPE_V32QI) -BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW, 0, CODE_FOR_vpopcountv32qi_mask, "__builtin_ia32_vpopcountb_v32qi_mask", IX86_BUILTIN_VPOPCOUNTBV32QI_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI) +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv32qi_mask, "__builtin_ia32_vpopcountb_v32qi_mask", IX86_BUILTIN_VPOPCOUNTBV32QI_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI) BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv16qi, "__builtin_ia32_vpopcountb_v16qi", IX86_BUILTIN_VPOPCOUNTBV16QI, UNKNOWN, (int) V16QI_FTYPE_V16QI) BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv16qi_mask, "__builtin_ia32_vpopcountb_v16qi_mask", IX86_BUILTIN_VPOPCOUNTBV16QI_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI) BDESC (OPTION_MASK_ISA_AVX512BITALG, 0, CODE_FOR_vpopcountv32hi, "__builtin_ia32_vpopcountw_v32hi", IX86_BUILTIN_VPOPCOUNTWV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI) -BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW, 0, CODE_FOR_vpopcountv32hi_mask, "__builtin_ia32_vpopcountw_v32hi_mask", IX86_BUILTIN_VPOPCOUNTQV32HI_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_USI) +BDESC (OPTION_MASK_ISA_AVX512BITALG, 0, CODE_FOR_vpopcountv32hi_mask, "__builtin_ia32_vpopcountw_v32hi_mask", IX86_BUILTIN_VPOPCOUNTQV32HI_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_USI) BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv16hi, "__builtin_ia32_vpopcountw_v16hi", IX86_BUILTIN_VPOPCOUNTWV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI) BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv16hi_mask, "__builtin_ia32_vpopcountw_v16hi_mask", IX86_BUILTIN_VPOPCOUNTQV16HI_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_UHI) BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv8hi, "__builtin_ia32_vpopcountw_v8hi", IX86_BUILTIN_VPOPCOUNTWV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI) BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpopcountv8hi_mask, "__builtin_ia32_vpopcountw_v8hi_mask", IX86_BUILTIN_VPOPCOUNTQV8HI_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_UQI) -BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW, 0, CODE_FOR_avx512vl_vpshufbitqmbv64qi_mask, "__builtin_ia32_vpshufbitqmb512_mask", IX86_BUILTIN_VPSHUFBITQMB512_MASK, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_UDI) -BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW, 0, CODE_FOR_avx512vl_vpshufbitqmbv32qi_mask, "__builtin_ia32_vpshufbitqmb256_mask", IX86_BUILTIN_VPSHUFBITQMB256_MASK, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_USI) +BDESC (OPTION_MASK_ISA_AVX512BITALG, 0, CODE_FOR_avx512vl_vpshufbitqmbv64qi_mask, "__builtin_ia32_vpshufbitqmb512_mask", IX86_BUILTIN_VPSHUFBITQMB512_MASK, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_UDI) +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_vpshufbitqmbv32qi_mask, "__builtin_ia32_vpshufbitqmb256_mask", IX86_BUILTIN_VPSHUFBITQMB256_MASK, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_USI) BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_vpshufbitqmbv16qi_mask, "__builtin_ia32_vpshufbitqmb128_mask", IX86_BUILTIN_VPSHUFBITQMB128_MASK, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_UHI) /* AVX512_4FMAPS and AVX512_4VNNIW builtins with variable number of arguments. Defined in additional ix86_isa_flags2. */ diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 5b6b2427460..deb2d747ec1 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -686,10 +686,6 @@ (define_mode_iterator VF4_128_8_256 [V4DF V4SF]) -(define_mode_iterator VI1_AVX512VLBW - [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX512VL") - (V16QI "TARGET_AVX512VL")]) - (define_mode_attr avx512 [(V16QI "avx512vl") (V32QI "avx512vl") (V64QI "avx512bw") (V8HI "avx512vl") (V16HI "avx512vl") (V32HI "avx512bw") @@ -28853,8 +28849,8 @@ (define_insn "avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>" [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k") (unspec:<avx512fmaskmode> - [(match_operand:VI1_AVX512VLBW 1 "register_operand" "v") - (match_operand:VI1_AVX512VLBW 2 "nonimmediate_operand" "vm")] + [(match_operand:VI1_AVX512VL 1 "register_operand" "v") + (match_operand:VI1_AVX512VL 2 "nonimmediate_operand" "vm")] UNSPEC_VPSHUFBIT))] "TARGET_AVX512BITALG" "vpshufbitqmb\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}" diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb-1.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb-1.c index 697757b8b73..93afe13227f 100644 --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb-1.c @@ -1,7 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mavx512bitalg -mavx512bw" } */ +/* { dg-options "-O2 -mavx512bitalg" } */ /* { dg-require-effective-target avx512bitalg } */ -/* { dg-require-effective-target avx512bw } */ #define AVX512BITALG #define SIZE (AVX512F_LEN / 8) diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb.c index 246f925eede..44b82c0519d 100644 --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb.c +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntb.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mavx512bitalg -mavx512bw" } */ +/* { dg-options "-O2 -mavx512bitalg" } */ /* { dg-final { scan-assembler-times "vpopcntb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpopcntb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpopcntb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntbvl.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntbvl.c index 8c7f45fc5f7..8c2dfaba9c6 100644 --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntbvl.c +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntbvl.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mavx512bitalg -mavx512bw -mavx512vl" } */ +/* { dg-options "-O2 -mavx512bitalg -mavx512vl" } */ /* { dg-final { scan-assembler-times "vpopcntb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpopcntb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpopcntb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw-1.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw-1.c index 0a725fe012a..93e2be23f1f 100644 --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw-1.c @@ -1,7 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mavx512bitalg -mavx512bw" } */ +/* { dg-options "-O2 -mavx512bitalg" } */ /* { dg-require-effective-target avx512bitalg } */ -/* { dg-require-effective-target avx512bw } */ #define AVX512BITALG #define SIZE (AVX512F_LEN / 16) diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw.c index 90663f480fc..2ef8589f6c1 100644 --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw.c +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntw.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mavx512bitalg -mavx512bw" } */ +/* { dg-options "-O2 -mavx512bitalg" } */ /* { dg-final { scan-assembler-times "vpopcntw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpopcntw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpopcntw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntwvl.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntwvl.c index 3a646b57282..c976461b12e 100644 --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntwvl.c +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpopcntwvl.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mavx512bitalg -mavx512bw -mavx512vl" } */ +/* { dg-options "-O2 -mavx512bitalg -mavx512vl" } */ /* { dg-final { scan-assembler-times "vpopcntw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpopcntw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpopcntw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c index 668064aa4e1..5e881484bde 100644 --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mavx512bitalg -mavx512f -mavx512bw" } */ +/* { dg-options "-O2 -mavx512bitalg" } */ /* { dg-require-effective-target avx512bitalg } */ #define AVX512BITALG diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb.c b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb.c index 7acb0c203f3..75fbef89732 100644 --- a/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb.c +++ b/gcc/testsuite/gcc.target/i386/avx512bitalg-vpshufbitqmb.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mavx512bitalg -mavx512vl -mavx512bw -O2" } */ +/* { dg-options "-mavx512bitalg -mavx512vl -O2" } */ /* { dg-final { scan-assembler-times "vpshufbitqmb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpshufbitqmb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vpshufbitqmb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntb-1.c b/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntb-1.c index 607ec3ff3df..a4e9d63fc1c 100644 --- a/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntb-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntb-1.c @@ -1,8 +1,7 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mavx512vl -mavx512bitalg -mavx512bw" } */ +/* { dg-options "-O2 -mavx512vl -mavx512bitalg" } */ /* { dg-require-effective-target avx512vl } */ /* { dg-require-effective-target avx512bitalg } */ -/* { dg-require-effective-target avx512bw } */ #define AVX512VL #define AVX512F_LEN 256 diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntw-1.c b/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntw-1.c index 3d7e2b5eb11..55fa811fb46 100644 --- a/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntw-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpopcntw-1.c @@ -1,8 +1,7 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mavx512vl -mavx512bitalg -mavx512bw" } */ +/* { dg-options "-O2 -mavx512vl -mavx512bitalg" } */ /* { dg-require-effective-target avx512vl } */ /* { dg-require-effective-target avx512bitalg } */ -/* { dg-require-effective-target avx512bw } */ #define AVX512VL #define AVX512F_LEN 256 diff --git a/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c b/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c index 76598c44946..497e369bf80 100644 --- a/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mavx512vl -mavx512bitalg -mavx512bw" } */ +/* { dg-options "-O2 -mavx512vl -mavx512bitalg" } */ /* { dg-require-effective-target avx512vl } */ /* { dg-require-effective-target avx512bitalg } */ diff --git a/gcc/testsuite/gcc.target/i386/pr93696-1.c b/gcc/testsuite/gcc.target/i386/pr93696-1.c index 128bb98c066..70f0f8ad8e1 100644 --- a/gcc/testsuite/gcc.target/i386/pr93696-1.c +++ b/gcc/testsuite/gcc.target/i386/pr93696-1.c @@ -1,6 +1,6 @@ /* PR target/93696 */ /* { dg-do compile } */ -/* { dg-options "-O2 -mavx512bitalg -mavx512vpopcntdq -mavx512vl -mavx512bw -masm=att" } */ +/* { dg-options "-O2 -mavx512bitalg -mavx512vpopcntdq -mavx512vl -masm=att" } */ /* { dg-final { scan-assembler-times "vpopcnt\[bwdq]\t%\[xyz]mm1, %\[xyz]mm0\{%k\[0-7]\}\[^\{]" 12 } } */ /* { dg-final { scan-assembler-not "vmovdq\[au]\[0-9]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr93696-2.c b/gcc/testsuite/gcc.target/i386/pr93696-2.c index 25a298aea18..e6aabd4d081 100644 --- a/gcc/testsuite/gcc.target/i386/pr93696-2.c +++ b/gcc/testsuite/gcc.target/i386/pr93696-2.c @@ -1,6 +1,6 @@ /* PR target/93696 */ /* { dg-do compile } */ -/* { dg-options "-O2 -mavx512bitalg -mavx512vpopcntdq -mavx512vl -mavx512bw -masm=att" } */ +/* { dg-options "-O2 -mavx512bitalg -mavx512vpopcntdq -mavx512vl -masm=att" } */ /* { dg-final { scan-assembler-times "vpopcnt\[bwdq]\t%\[xyz]mm1, %\[xyz]mm0\{%k\[0-7]\}\{z\}" 12 } } */ /* { dg-final { scan-assembler-not "vmovdq\[au]\[0-9]" } } */