@@ -115,9 +115,16 @@
UNSPEC_COMPARE_AND_SWAP))
(clobber (match_scratch:GPR 6 "=&r"))]
"TARGET_ATOMIC"
- "%F5 1: lr.<amo>%A5 %0,%1; bne %0,%z2,1f; sc.<amo>%A4 %6,%z3,%1; bnez %6,1b; 1:"
+ {
+ return "1:\;"
+ "lr.<amo>.aqrl\t%0,%1\;"
+ "bne\t%0,%z2,1f\;"
+ "sc.<amo>.rl\t%6,%z3,%1\;"
+ "bnez\t%6,1b\;"
+ "1:";
+ }
[(set_attr "type" "atomic")
- (set (attr "length") (const_int 20))])
+ (set (attr "length") (const_int 16))])
(define_expand "atomic_compare_and_swap<mode>"
[(match_operand:SI 0 "register_operand" "") ;; bool output
This patch enforces SEQ_CST for atomic compare_exchange ops. Replace Fence/LR.aq/SC.aq pairs with strong SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-05 Patrick O'Neill <patrick@rivosinc.com> * sync.md: Change FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl pair. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com> --- gcc/config/riscv/sync.md | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)