diff mbox series

RISC-V: Fix typo

Message ID 20230403011939.10677-1-xuli1@eswincomputing.com
State New
Headers show
Series RISC-V: Fix typo | expand

Commit Message

Li Xu April 3, 2023, 1:19 a.m. UTC 
gcc/ChangeLog:

        * config/riscv/riscv-vector-builtins.def (vuint32m8_t): Fix typo
        (vfloat32m8_t): Likewise
---
 gcc/config/riscv/riscv-vector-builtins.def | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Jeff Law April 3, 2023, 4 a.m. UTC | #1 
On 4/2/23 19:19, Li Xu wrote:
> gcc/ChangeLog:
> 
>          * config/riscv/riscv-vector-builtins.def (vuint32m8_t): Fix typo
>          (vfloat32m8_t): Likewise
THanks.  Pushed to the trunk.
jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
index d4a74befd8a..2d527f76f0a 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -234,7 +234,7 @@  DEF_RVV_TYPE (vuint32m8_t, 16, __rvv_uint32m8_t, uint32, VNx16SI, VNx8SI,
 	      _u32m8, _u32, _e32m8)
 
 /* SEW = 64:
-   Disable when TARGET_MIN_VLEN > 32.  */
+   Enable when TARGET_MIN_VLEN > 32.  */
 DEF_RVV_TYPE (vint64m1_t, 15, __rvv_int64m1_t, int64, VNx1DI, VOID, _i64m1,
 	      _i64, _e64m1)
 DEF_RVV_TYPE (vuint64m1_t, 16, __rvv_uint64m1_t, uint64, VNx1DI, VOID, _u64m1,
@@ -278,7 +278,7 @@  DEF_RVV_TYPE (vfloat32m8_t, 17, __rvv_float32m8_t, float, VNx16SF, VNx8SF,
 	      _f32m8, _f32, _e32m8)
 
 /* SEW = 64:
-   Disable when TARGET_VECTOR_FP64.  */
+   Enable when TARGET_VECTOR_FP64.  */
 DEF_RVV_TYPE (vfloat64m1_t, 17, __rvv_float64m1_t, double, VNx1DF, VOID, _f64m1,
 	      _f64, _e64m1)
 DEF_RVV_TYPE (vfloat64m2_t, 17, __rvv_float64m2_t, double, VNx2DF, VOID, _f64m2,