From patchwork Thu Feb 16 03:40:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 1743298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PHLLs5nFXz1yYg for ; Thu, 16 Feb 2023 14:40:36 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E933E3857BA4 for ; Thu, 16 Feb 2023 03:40:33 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id 93C9F3857BA4 for ; Thu, 16 Feb 2023 03:40:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 93C9F3857BA4 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp69t1676518802t3krcubo Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 16 Feb 2023 11:40:02 +0800 (CST) X-QQ-SSF: 01400000000000E0M000000A0000000 X-QQ-FEAT: LG+NUo/f6sGirk2gTQJOV0m0cjM4cOQDMZTiBlf8kQ4z9xw6sjQiuwL8DsqOr Zi7C/kAfN1xHirFH0C7epTYTmKz9aq8U4XU/FhNurigO7DtZH6D7AVN9oUaV7ctls+8KqXE UbWdKgEG98RV1Lfcw2uNEtJpcajLhs/vW8TQpDSnztz4mdfOdwiUSNJEzKOnEpUCeAalBCA oQ1ZsUoS1oDNpQgK03cyicwyK1vilYkVl3+c+QbZESept9QYZbOpCAMkCsq1PGd/9AwpcfQ QtF2/Sgn2TGPxzly5RqsYaiC+oDPt91eg8HAJ0t3Hl0QbSal088xm0ARo6CrvHn7vesmQCJ pUMq9RPPk2OTqA3/d+9sJEWwL1KCst9X+zN/UdhEguKVKz50Xvnod4/UjpEmA== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add the res of all mask C api tests Date: Thu, 16 Feb 2023 11:40:01 +0800 Message-Id: <20230216034001.17197-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vcpop_m_m-1.c: New test. * gcc.target/riscv/rvv/base/vcpop_m_m-2.c: New test. * gcc.target/riscv/rvv/base/vcpop_m_m-3.c: New test. * gcc.target/riscv/rvv/base/vfirst_m_m-1.c: New test. * gcc.target/riscv/rvv/base/vfirst_m_m-2.c: New test. * gcc.target/riscv/rvv/base/vfirst_m_m-3.c: New test. * gcc.target/riscv/rvv/base/vlm_v-1.c: New test. * gcc.target/riscv/rvv/base/vlm_v-2.c: New test. * gcc.target/riscv/rvv/base/vlm_v-3.c: New test. * gcc.target/riscv/rvv/base/vsm_v-1.c: New test. * gcc.target/riscv/rvv/base/vsm_v-2.c: New test. * gcc.target/riscv/rvv/base/vsm_v-3.c: New test. --- .../gcc.target/riscv/rvv/base/vcpop_m_m-1.c | 104 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vcpop_m_m-2.c | 104 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vcpop_m_m-3.c | 104 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vfirst_m_m-1.c | 104 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vfirst_m_m-2.c | 104 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vfirst_m_m-3.c | 104 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vlm_v-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vlm_v-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vlm_v-3.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vsm_v-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vsm_v-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vsm_v-3.c | 55 +++++++++ 12 files changed, 954 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-1.c new file mode 100644 index 00000000000..5ac335ac1ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +uint64_t test___riscv_vcpop_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vcpop_m_b1(op1,vl); +} + + +uint64_t test___riscv_vcpop_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vcpop_m_b2(op1,vl); +} + + +uint64_t test___riscv_vcpop_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vcpop_m_b4(op1,vl); +} + + +uint64_t test___riscv_vcpop_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vcpop_m_b8(op1,vl); +} + + +uint64_t test___riscv_vcpop_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vcpop_m_b16(op1,vl); +} + + +uint64_t test___riscv_vcpop_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vcpop_m_b32(op1,vl); +} + + +uint64_t test___riscv_vcpop_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vcpop_m_b64(op1,vl); +} + + +uint64_t test___riscv_vcpop_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vcpop_m_b1_m(mask,op1,vl); +} + + +uint64_t test___riscv_vcpop_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vcpop_m_b2_m(mask,op1,vl); +} + + +uint64_t test___riscv_vcpop_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vcpop_m_b4_m(mask,op1,vl); +} + + +uint64_t test___riscv_vcpop_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vcpop_m_b8_m(mask,op1,vl); +} + + +uint64_t test___riscv_vcpop_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vcpop_m_b16_m(mask,op1,vl); +} + + +uint64_t test___riscv_vcpop_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vcpop_m_b32_m(mask,op1,vl); +} + + +uint64_t test___riscv_vcpop_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vcpop_m_b64_m(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-2.c new file mode 100644 index 00000000000..76c3ce31e39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-2.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +uint64_t test___riscv_vcpop_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vcpop_m_b1(op1,31); +} + + +uint64_t test___riscv_vcpop_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vcpop_m_b2(op1,31); +} + + +uint64_t test___riscv_vcpop_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vcpop_m_b4(op1,31); +} + + +uint64_t test___riscv_vcpop_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vcpop_m_b8(op1,31); +} + + +uint64_t test___riscv_vcpop_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vcpop_m_b16(op1,31); +} + + +uint64_t test___riscv_vcpop_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vcpop_m_b32(op1,31); +} + + +uint64_t test___riscv_vcpop_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vcpop_m_b64(op1,31); +} + + +uint64_t test___riscv_vcpop_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vcpop_m_b1_m(mask,op1,31); +} + + +uint64_t test___riscv_vcpop_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vcpop_m_b2_m(mask,op1,31); +} + + +uint64_t test___riscv_vcpop_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vcpop_m_b4_m(mask,op1,31); +} + + +uint64_t test___riscv_vcpop_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vcpop_m_b8_m(mask,op1,31); +} + + +uint64_t test___riscv_vcpop_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vcpop_m_b16_m(mask,op1,31); +} + + +uint64_t test___riscv_vcpop_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vcpop_m_b32_m(mask,op1,31); +} + + +uint64_t test___riscv_vcpop_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vcpop_m_b64_m(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-3.c new file mode 100644 index 00000000000..eeab2c000e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-3.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +uint64_t test___riscv_vcpop_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vcpop_m_b1(op1,32); +} + + +uint64_t test___riscv_vcpop_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vcpop_m_b2(op1,32); +} + + +uint64_t test___riscv_vcpop_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vcpop_m_b4(op1,32); +} + + +uint64_t test___riscv_vcpop_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vcpop_m_b8(op1,32); +} + + +uint64_t test___riscv_vcpop_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vcpop_m_b16(op1,32); +} + + +uint64_t test___riscv_vcpop_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vcpop_m_b32(op1,32); +} + + +uint64_t test___riscv_vcpop_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vcpop_m_b64(op1,32); +} + + +uint64_t test___riscv_vcpop_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vcpop_m_b1_m(mask,op1,32); +} + + +uint64_t test___riscv_vcpop_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vcpop_m_b2_m(mask,op1,32); +} + + +uint64_t test___riscv_vcpop_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vcpop_m_b4_m(mask,op1,32); +} + + +uint64_t test___riscv_vcpop_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vcpop_m_b8_m(mask,op1,32); +} + + +uint64_t test___riscv_vcpop_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vcpop_m_b16_m(mask,op1,32); +} + + +uint64_t test___riscv_vcpop_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vcpop_m_b32_m(mask,op1,32); +} + + +uint64_t test___riscv_vcpop_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vcpop_m_b64_m(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-1.c new file mode 100644 index 00000000000..13631233a12 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +long test___riscv_vfirst_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vfirst_m_b1(op1,vl); +} + + +long test___riscv_vfirst_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vfirst_m_b2(op1,vl); +} + + +long test___riscv_vfirst_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vfirst_m_b4(op1,vl); +} + + +long test___riscv_vfirst_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vfirst_m_b8(op1,vl); +} + + +long test___riscv_vfirst_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vfirst_m_b16(op1,vl); +} + + +long test___riscv_vfirst_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vfirst_m_b32(op1,vl); +} + + +long test___riscv_vfirst_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vfirst_m_b64(op1,vl); +} + + +long test___riscv_vfirst_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vfirst_m_b1_m(mask,op1,vl); +} + + +long test___riscv_vfirst_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vfirst_m_b2_m(mask,op1,vl); +} + + +long test___riscv_vfirst_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vfirst_m_b4_m(mask,op1,vl); +} + + +long test___riscv_vfirst_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vfirst_m_b8_m(mask,op1,vl); +} + + +long test___riscv_vfirst_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vfirst_m_b16_m(mask,op1,vl); +} + + +long test___riscv_vfirst_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vfirst_m_b32_m(mask,op1,vl); +} + + +long test___riscv_vfirst_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vfirst_m_b64_m(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-2.c new file mode 100644 index 00000000000..bd68d048aff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-2.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +long test___riscv_vfirst_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vfirst_m_b1(op1,31); +} + + +long test___riscv_vfirst_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vfirst_m_b2(op1,31); +} + + +long test___riscv_vfirst_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vfirst_m_b4(op1,31); +} + + +long test___riscv_vfirst_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vfirst_m_b8(op1,31); +} + + +long test___riscv_vfirst_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vfirst_m_b16(op1,31); +} + + +long test___riscv_vfirst_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vfirst_m_b32(op1,31); +} + + +long test___riscv_vfirst_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vfirst_m_b64(op1,31); +} + + +long test___riscv_vfirst_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vfirst_m_b1_m(mask,op1,31); +} + + +long test___riscv_vfirst_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vfirst_m_b2_m(mask,op1,31); +} + + +long test___riscv_vfirst_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vfirst_m_b4_m(mask,op1,31); +} + + +long test___riscv_vfirst_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vfirst_m_b8_m(mask,op1,31); +} + + +long test___riscv_vfirst_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vfirst_m_b16_m(mask,op1,31); +} + + +long test___riscv_vfirst_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vfirst_m_b32_m(mask,op1,31); +} + + +long test___riscv_vfirst_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vfirst_m_b64_m(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-3.c new file mode 100644 index 00000000000..641e4fa2982 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-3.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +long test___riscv_vfirst_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vfirst_m_b1(op1,32); +} + + +long test___riscv_vfirst_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vfirst_m_b2(op1,32); +} + + +long test___riscv_vfirst_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vfirst_m_b4(op1,32); +} + + +long test___riscv_vfirst_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vfirst_m_b8(op1,32); +} + + +long test___riscv_vfirst_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vfirst_m_b16(op1,32); +} + + +long test___riscv_vfirst_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vfirst_m_b32(op1,32); +} + + +long test___riscv_vfirst_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vfirst_m_b64(op1,32); +} + + +long test___riscv_vfirst_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vfirst_m_b1_m(mask,op1,32); +} + + +long test___riscv_vfirst_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vfirst_m_b2_m(mask,op1,32); +} + + +long test___riscv_vfirst_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vfirst_m_b4_m(mask,op1,32); +} + + +long test___riscv_vfirst_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vfirst_m_b8_m(mask,op1,32); +} + + +long test___riscv_vfirst_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vfirst_m_b16_m(mask,op1,32); +} + + +long test___riscv_vfirst_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vfirst_m_b32_m(mask,op1,32); +} + + +long test___riscv_vfirst_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vfirst_m_b64_m(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-1.c new file mode 100644 index 00000000000..87f73b868c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vlm_v_b1(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b1(base,vl); +} + + +vbool2_t test___riscv_vlm_v_b2(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b2(base,vl); +} + + +vbool4_t test___riscv_vlm_v_b4(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b4(base,vl); +} + + +vbool8_t test___riscv_vlm_v_b8(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b8(base,vl); +} + + +vbool16_t test___riscv_vlm_v_b16(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b16(base,vl); +} + + +vbool32_t test___riscv_vlm_v_b32(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b32(base,vl); +} + + +vbool64_t test___riscv_vlm_v_b64(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b64(base,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-2.c new file mode 100644 index 00000000000..662ac7e4002 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vlm_v_b1(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b1(base,31); +} + + +vbool2_t test___riscv_vlm_v_b2(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b2(base,31); +} + + +vbool4_t test___riscv_vlm_v_b4(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b4(base,31); +} + + +vbool8_t test___riscv_vlm_v_b8(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b8(base,31); +} + + +vbool16_t test___riscv_vlm_v_b16(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b16(base,31); +} + + +vbool32_t test___riscv_vlm_v_b32(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b32(base,31); +} + + +vbool64_t test___riscv_vlm_v_b64(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b64(base,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-3.c new file mode 100644 index 00000000000..edac4f70a6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vlm_v_b1(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b1(base,32); +} + + +vbool2_t test___riscv_vlm_v_b2(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b2(base,32); +} + + +vbool4_t test___riscv_vlm_v_b4(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b4(base,32); +} + + +vbool8_t test___riscv_vlm_v_b8(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b8(base,32); +} + + +vbool16_t test___riscv_vlm_v_b16(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b16(base,32); +} + + +vbool32_t test___riscv_vlm_v_b32(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b32(base,32); +} + + +vbool64_t test___riscv_vlm_v_b64(const uint8_t* base,size_t vl) +{ + return __riscv_vlm_v_b64(base,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-1.c new file mode 100644 index 00000000000..ff158c86b23 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +void test___riscv_vsm_v_b1(uint8_t* base,vbool1_t value,size_t vl) +{ + __riscv_vsm_v_b1(base,value,vl); +} + + +void test___riscv_vsm_v_b2(uint8_t* base,vbool2_t value,size_t vl) +{ + __riscv_vsm_v_b2(base,value,vl); +} + + +void test___riscv_vsm_v_b4(uint8_t* base,vbool4_t value,size_t vl) +{ + __riscv_vsm_v_b4(base,value,vl); +} + + +void test___riscv_vsm_v_b8(uint8_t* base,vbool8_t value,size_t vl) +{ + __riscv_vsm_v_b8(base,value,vl); +} + + +void test___riscv_vsm_v_b16(uint8_t* base,vbool16_t value,size_t vl) +{ + __riscv_vsm_v_b16(base,value,vl); +} + + +void test___riscv_vsm_v_b32(uint8_t* base,vbool32_t value,size_t vl) +{ + __riscv_vsm_v_b32(base,value,vl); +} + + +void test___riscv_vsm_v_b64(uint8_t* base,vbool64_t value,size_t vl) +{ + __riscv_vsm_v_b64(base,value,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-2.c new file mode 100644 index 00000000000..15a3575e3d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +void test___riscv_vsm_v_b1(uint8_t* base,vbool1_t value,size_t vl) +{ + __riscv_vsm_v_b1(base,value,31); +} + + +void test___riscv_vsm_v_b2(uint8_t* base,vbool2_t value,size_t vl) +{ + __riscv_vsm_v_b2(base,value,31); +} + + +void test___riscv_vsm_v_b4(uint8_t* base,vbool4_t value,size_t vl) +{ + __riscv_vsm_v_b4(base,value,31); +} + + +void test___riscv_vsm_v_b8(uint8_t* base,vbool8_t value,size_t vl) +{ + __riscv_vsm_v_b8(base,value,31); +} + + +void test___riscv_vsm_v_b16(uint8_t* base,vbool16_t value,size_t vl) +{ + __riscv_vsm_v_b16(base,value,31); +} + + +void test___riscv_vsm_v_b32(uint8_t* base,vbool32_t value,size_t vl) +{ + __riscv_vsm_v_b32(base,value,31); +} + + +void test___riscv_vsm_v_b64(uint8_t* base,vbool64_t value,size_t vl) +{ + __riscv_vsm_v_b64(base,value,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-3.c new file mode 100644 index 00000000000..903303e166a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +void test___riscv_vsm_v_b1(uint8_t* base,vbool1_t value,size_t vl) +{ + __riscv_vsm_v_b1(base,value,32); +} + + +void test___riscv_vsm_v_b2(uint8_t* base,vbool2_t value,size_t vl) +{ + __riscv_vsm_v_b2(base,value,32); +} + + +void test___riscv_vsm_v_b4(uint8_t* base,vbool4_t value,size_t vl) +{ + __riscv_vsm_v_b4(base,value,32); +} + + +void test___riscv_vsm_v_b8(uint8_t* base,vbool8_t value,size_t vl) +{ + __riscv_vsm_v_b8(base,value,32); +} + + +void test___riscv_vsm_v_b16(uint8_t* base,vbool16_t value,size_t vl) +{ + __riscv_vsm_v_b16(base,value,32); +} + + +void test___riscv_vsm_v_b32(uint8_t* base,vbool32_t value,size_t vl) +{ + __riscv_vsm_v_b32(base,value,32); +} + + +void test___riscv_vsm_v_b64(uint8_t* base,vbool64_t value,size_t vl) +{ + __riscv_vsm_v_b64(base,value,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */