From patchwork Tue Feb 14 15:04:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 1742442 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PGPdl11RWz23r4 for ; Wed, 15 Feb 2023 02:05:14 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5FF073858291 for ; Tue, 14 Feb 2023 15:05:11 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) by sourceware.org (Postfix) with ESMTPS id 791CB3858D33 for ; Tue, 14 Feb 2023 15:04:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 791CB3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp91t1676387091th3f2yyz Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 14 Feb 2023 23:04:50 +0800 (CST) X-QQ-SSF: 01400000002000E0L000B00A0000000 X-QQ-FEAT: +ynUkgUhZJkf4jMwcmJ3B5tkXTIMn5WOHbwfem5oxYrLKeQ/fGGX7DrG2QLnX kFhShubkYjrqnaNqW7lKYd7CXqpOL3O9cv8ZHVZtitANutDABsLWIIV3PbjMDU4bXqX5ish xkVKXhV6A/J3Pr/Ph4rexutbjrePBXI82omfxmKFWLo41B90qoHXcqJXXtQZWu/GMYr28u7 jonKrWhS+dKk/NgHUAC/fIxdzWh9keP9TYuKXQbiYI8fyh101m/XrmhsnY/hpPN6mLXuJMC c0yCY+ak287xt/qYO8APbDxLP1QVQtEdAroxU6U4VYfRfdw3I4gLiTN/s4p3b6uxEivTjKn QjKG+j7tvEpdNnjf6shBoxCFHTKt0GEyQYL+CHGHNUrbLAPs/O9i+SUqvJIThrVdTZiCNAW w2pvUfhBF6w= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Replace simm32_p with immediate_operand (Pmode) Date: Tue, 14 Feb 2023 23:04:49 +0800 Message-Id: <20230214150449.249991-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong simm32_p is used to check constant int value within 32-bit. It's used in handling SEW = 64 in rv32 system since such constant int value with 32-bit allow us use vx instruction. The current implementation of simm32_p is quite ugly and now I figure out immedate_operand (op, pmode) can help us to check whether the op is a constant value within 32-bit. I already have a bunch testcases to test SEW = 64 in rv32 system and all regression tests are passed with this patch. gcc/ChangeLog: * config/riscv/riscv-protos.h (simm32_p): * config/riscv/riscv-v.cc (simm32_p): * config/riscv/vector.md: --- gcc/config/riscv/riscv-protos.h | 1 - gcc/config/riscv/riscv-v.cc | 10 ---------- gcc/config/riscv/vector.md | 34 ++++++++++++++++----------------- 3 files changed, 17 insertions(+), 28 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 9d8b0b78a06..ee8e903ddf5 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -176,7 +176,6 @@ enum tail_policy get_prefer_tail_policy (); enum mask_policy get_prefer_mask_policy (); rtx get_avl_type_rtx (enum avl_type); opt_machine_mode get_vector_mode (scalar_mode, poly_uint64); -extern bool simm32_p (rtx); extern bool simm5_p (rtx); extern bool neg_simm5_p (rtx); #ifdef RTX_CODE diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 600b2e6ecad..dd70bf9b541 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -396,16 +396,6 @@ get_vector_mode (scalar_mode inner_mode, poly_uint64 nunits) return opt_machine_mode (); } -/* Helper functions for handling sew=64 on RV32 system. */ -bool -simm32_p (rtx x) -{ - if (!CONST_INT_P (x)) - return false; - unsigned HOST_WIDE_INT val = UINTVAL (x); - return val <= 0x7FFFFFFFULL || val >= 0xFFFFFFFF80000000ULL; -} - bool simm5_p (rtx x) { diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index dc79aa230bd..b6e67e94f67 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -889,7 +889,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[3])) + if (immediate_operand (operands[3], Pmode)) operands[3] = gen_rtx_SIGN_EXTEND (mode, force_reg (Pmode, operands[3])); else @@ -1479,7 +1479,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[4])) + if (immediate_operand (operands[4], Pmode)) { if (!rtx_equal_p (operands[4], const0_rtx)) operands[4] = force_reg (Pmode, operands[4]); @@ -1572,7 +1572,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[4])) + if (immediate_operand (operands[4], Pmode)) { if (!rtx_equal_p (operands[4], const0_rtx)) operands[4] = force_reg (Pmode, operands[4]); @@ -1665,7 +1665,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[4])) + if (immediate_operand (operands[4], Pmode)) operands[4] = gen_rtx_SIGN_EXTEND (mode, force_reg (Pmode, operands[4])); else @@ -1820,7 +1820,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[4])) + if (immediate_operand (operands[4], Pmode)) operands[4] = gen_rtx_SIGN_EXTEND (mode, force_reg (Pmode, operands[4])); else @@ -1907,7 +1907,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[4])) + if (immediate_operand (operands[4], Pmode)) operands[4] = gen_rtx_SIGN_EXTEND (mode, force_reg (Pmode, operands[4])); else @@ -2034,7 +2034,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[4])) + if (immediate_operand (operands[4], Pmode)) { if (!rtx_equal_p (operands[4], const0_rtx)) operands[4] = force_reg (Pmode, operands[4]); @@ -2226,7 +2226,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[3])) + if (immediate_operand (operands[3], Pmode)) operands[3] = gen_rtx_SIGN_EXTEND (mode, force_reg (Pmode, operands[3])); else @@ -2320,7 +2320,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[3])) + if (immediate_operand (operands[3], Pmode)) { if (!rtx_equal_p (operands[3], const0_rtx)) operands[3] = force_reg (Pmode, operands[3]); @@ -2497,7 +2497,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[2])) + if (immediate_operand (operands[2], Pmode)) operands[2] = gen_rtx_SIGN_EXTEND (mode, force_reg (Pmode, operands[2])); else @@ -2577,7 +2577,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[2])) + if (immediate_operand (operands[2], Pmode)) { if (!rtx_equal_p (operands[2], const0_rtx)) operands[2] = force_reg (Pmode, operands[2]); @@ -2738,7 +2738,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[2])) + if (immediate_operand (operands[2], Pmode)) operands[2] = gen_rtx_SIGN_EXTEND (mode, force_reg (Pmode, operands[2])); else @@ -2815,7 +2815,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[2])) + if (immediate_operand (operands[2], Pmode)) { if (!rtx_equal_p (operands[2], const0_rtx)) operands[2] = force_reg (Pmode, operands[2]); @@ -3310,7 +3310,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[4])) + if (immediate_operand (operands[4], Pmode)) { if (!rtx_equal_p (operands[4], const0_rtx)) operands[4] = force_reg (Pmode, operands[4]); @@ -3686,7 +3686,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[5])) + if (immediate_operand (operands[5], Pmode)) { if (!rtx_equal_p (operands[5], const0_rtx)) operands[5] = force_reg (Pmode, operands[5]); @@ -3739,7 +3739,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[5])) + if (immediate_operand (operands[5], Pmode)) { if (!rtx_equal_p (operands[5], const0_rtx)) operands[5] = force_reg (Pmode, operands[5]); @@ -4404,7 +4404,7 @@ { rtx v = gen_reg_rtx (mode); - if (riscv_vector::simm32_p (operands[2])) + if (immediate_operand (operands[2], Pmode)) operands[2] = gen_rtx_SIGN_EXTEND (mode, force_reg (Pmode, operands[2])); else