diff mbox series

RISC-V: Add vncvt/vmv C++ API tests

Message ID 20230209220103.28557-1-juzhe.zhong@rivai.ai
State New
Headers show
Series RISC-V: Add vncvt/vmv C++ API tests | expand

Commit Message

juzhe.zhong@rivai.ai Feb. 9, 2023, 10:01 p.m. UTC 
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vmv_v-1.C: New test.
        * g++.target/riscv/rvv/base/vmv_v_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vmv_v_x_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmv_v_x_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmv_v_x_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmv_v_x_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmv_v_x_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmv_v_x_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vncvt_x-1.C: New test.
        * g++.target/riscv/rvv/base/vncvt_x-2.C: New test.
        * g++.target/riscv/rvv/base/vncvt_x-3.C: New test.
        * g++.target/riscv/rvv/base/vncvt_x_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vncvt_x_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vncvt_x_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vncvt_x_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vncvt_x_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vncvt_x_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vncvt_x_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vncvt_x_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vncvt_x_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vncvt_x_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vncvt_x_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vncvt_x_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vmv_v-1.C       | 392 +++++++++++++++++
 .../g++.target/riscv/rvv/base/vmv_v_tu-1.C    | 392 +++++++++++++++++
 .../riscv/rvv/base/vmv_v_x_rv32-1.C           | 289 +++++++++++++
 .../riscv/rvv/base/vmv_v_x_rv32-2.C           | 289 +++++++++++++
 .../riscv/rvv/base/vmv_v_x_rv32-3.C           | 289 +++++++++++++
 .../riscv/rvv/base/vmv_v_x_rv64-1.C           | 292 +++++++++++++
 .../riscv/rvv/base/vmv_v_x_rv64-2.C           | 292 +++++++++++++
 .../riscv/rvv/base/vmv_v_x_rv64-3.C           | 292 +++++++++++++
 .../g++.target/riscv/rvv/base/vncvt_x-1.C     | 396 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vncvt_x-2.C     | 396 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vncvt_x-3.C     | 396 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vncvt_x_mu-1.C  | 201 +++++++++
 .../g++.target/riscv/rvv/base/vncvt_x_mu-2.C  | 201 +++++++++
 .../g++.target/riscv/rvv/base/vncvt_x_mu-3.C  | 201 +++++++++
 .../g++.target/riscv/rvv/base/vncvt_x_tu-1.C  | 201 +++++++++
 .../g++.target/riscv/rvv/base/vncvt_x_tu-2.C  | 201 +++++++++
 .../g++.target/riscv/rvv/base/vncvt_x_tu-3.C  | 201 +++++++++
 .../g++.target/riscv/rvv/base/vncvt_x_tum-1.C | 201 +++++++++
 .../g++.target/riscv/rvv/base/vncvt_x_tum-2.C | 201 +++++++++
 .../g++.target/riscv/rvv/base/vncvt_x_tum-3.C | 201 +++++++++
 .../riscv/rvv/base/vncvt_x_tumu-1.C           | 201 +++++++++
 .../riscv/rvv/base/vncvt_x_tumu-2.C           | 201 +++++++++
 .../riscv/rvv/base/vncvt_x_tumu-3.C           | 201 +++++++++
 23 files changed, 6127 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-3.C
diff mbox series

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v-1.C
new file mode 100644
index 00000000000..fcda5352b63
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v-1.C
@@ -0,0 +1,392 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test_vmv_v_v_i8mf8_tu(vint8mf8_t maskedoff, vint8mf8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8mf8_t test_vmv_v_x_i8mf8_tu(vint8mf8_t maskedoff, int8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8mf4_t test_vmv_v_v_i8mf4_tu(vint8mf4_t maskedoff, vint8mf4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8mf4_t test_vmv_v_x_i8mf4_tu(vint8mf4_t maskedoff, int8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8mf2_t test_vmv_v_v_i8mf2_tu(vint8mf2_t maskedoff, vint8mf2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8mf2_t test_vmv_v_x_i8mf2_tu(vint8mf2_t maskedoff, int8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m1_t test_vmv_v_v_i8m1_tu(vint8m1_t maskedoff, vint8m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m1_t test_vmv_v_x_i8m1_tu(vint8m1_t maskedoff, int8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m2_t test_vmv_v_v_i8m2_tu(vint8m2_t maskedoff, vint8m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m2_t test_vmv_v_x_i8m2_tu(vint8m2_t maskedoff, int8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m4_t test_vmv_v_v_i8m4_tu(vint8m4_t maskedoff, vint8m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m4_t test_vmv_v_x_i8m4_tu(vint8m4_t maskedoff, int8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m8_t test_vmv_v_v_i8m8_tu(vint8m8_t maskedoff, vint8m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m8_t test_vmv_v_x_i8m8_tu(vint8m8_t maskedoff, int8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16mf4_t test_vmv_v_v_i16mf4_tu(vint16mf4_t maskedoff, vint16mf4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16mf4_t test_vmv_v_x_i16mf4_tu(vint16mf4_t maskedoff, int16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16mf2_t test_vmv_v_v_i16mf2_tu(vint16mf2_t maskedoff, vint16mf2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16mf2_t test_vmv_v_x_i16mf2_tu(vint16mf2_t maskedoff, int16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m1_t test_vmv_v_v_i16m1_tu(vint16m1_t maskedoff, vint16m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m1_t test_vmv_v_x_i16m1_tu(vint16m1_t maskedoff, int16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m2_t test_vmv_v_v_i16m2_tu(vint16m2_t maskedoff, vint16m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m2_t test_vmv_v_x_i16m2_tu(vint16m2_t maskedoff, int16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m4_t test_vmv_v_v_i16m4_tu(vint16m4_t maskedoff, vint16m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m4_t test_vmv_v_x_i16m4_tu(vint16m4_t maskedoff, int16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m8_t test_vmv_v_v_i16m8_tu(vint16m8_t maskedoff, vint16m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m8_t test_vmv_v_x_i16m8_tu(vint16m8_t maskedoff, int16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32mf2_t test_vmv_v_v_i32mf2_tu(vint32mf2_t maskedoff, vint32mf2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32mf2_t test_vmv_v_x_i32mf2_tu(vint32mf2_t maskedoff, int32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m1_t test_vmv_v_v_i32m1_tu(vint32m1_t maskedoff, vint32m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m1_t test_vmv_v_x_i32m1_tu(vint32m1_t maskedoff, int32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m2_t test_vmv_v_v_i32m2_tu(vint32m2_t maskedoff, vint32m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m2_t test_vmv_v_x_i32m2_tu(vint32m2_t maskedoff, int32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m4_t test_vmv_v_v_i32m4_tu(vint32m4_t maskedoff, vint32m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m4_t test_vmv_v_x_i32m4_tu(vint32m4_t maskedoff, int32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m8_t test_vmv_v_v_i32m8_tu(vint32m8_t maskedoff, vint32m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m8_t test_vmv_v_x_i32m8_tu(vint32m8_t maskedoff, int32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m1_t test_vmv_v_v_i64m1_tu(vint64m1_t maskedoff, vint64m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m1_t test_vmv_v_x_i64m1_tu(vint64m1_t maskedoff, int64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m2_t test_vmv_v_v_i64m2_tu(vint64m2_t maskedoff, vint64m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m2_t test_vmv_v_x_i64m2_tu(vint64m2_t maskedoff, int64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m4_t test_vmv_v_v_i64m4_tu(vint64m4_t maskedoff, vint64m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m4_t test_vmv_v_x_i64m4_tu(vint64m4_t maskedoff, int64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m8_t test_vmv_v_v_i64m8_tu(vint64m8_t maskedoff, vint64m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m8_t test_vmv_v_x_i64m8_tu(vint64m8_t maskedoff, int64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8mf8_t test_vmv_v_v_u8mf8_tu(vuint8mf8_t maskedoff, vuint8mf8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8mf8_t test_vmv_v_x_u8mf8_tu(vuint8mf8_t maskedoff, uint8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8mf4_t test_vmv_v_v_u8mf4_tu(vuint8mf4_t maskedoff, vuint8mf4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8mf4_t test_vmv_v_x_u8mf4_tu(vuint8mf4_t maskedoff, uint8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8mf2_t test_vmv_v_v_u8mf2_tu(vuint8mf2_t maskedoff, vuint8mf2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8mf2_t test_vmv_v_x_u8mf2_tu(vuint8mf2_t maskedoff, uint8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m1_t test_vmv_v_v_u8m1_tu(vuint8m1_t maskedoff, vuint8m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m1_t test_vmv_v_x_u8m1_tu(vuint8m1_t maskedoff, uint8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m2_t test_vmv_v_v_u8m2_tu(vuint8m2_t maskedoff, vuint8m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m2_t test_vmv_v_x_u8m2_tu(vuint8m2_t maskedoff, uint8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m4_t test_vmv_v_v_u8m4_tu(vuint8m4_t maskedoff, vuint8m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m4_t test_vmv_v_x_u8m4_tu(vuint8m4_t maskedoff, uint8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m8_t test_vmv_v_v_u8m8_tu(vuint8m8_t maskedoff, vuint8m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m8_t test_vmv_v_x_u8m8_tu(vuint8m8_t maskedoff, uint8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16mf4_t test_vmv_v_v_u16mf4_tu(vuint16mf4_t maskedoff, vuint16mf4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16mf4_t test_vmv_v_x_u16mf4_tu(vuint16mf4_t maskedoff, uint16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16mf2_t test_vmv_v_v_u16mf2_tu(vuint16mf2_t maskedoff, vuint16mf2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16mf2_t test_vmv_v_x_u16mf2_tu(vuint16mf2_t maskedoff, uint16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m1_t test_vmv_v_v_u16m1_tu(vuint16m1_t maskedoff, vuint16m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m1_t test_vmv_v_x_u16m1_tu(vuint16m1_t maskedoff, uint16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m2_t test_vmv_v_v_u16m2_tu(vuint16m2_t maskedoff, vuint16m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m2_t test_vmv_v_x_u16m2_tu(vuint16m2_t maskedoff, uint16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m4_t test_vmv_v_v_u16m4_tu(vuint16m4_t maskedoff, vuint16m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m4_t test_vmv_v_x_u16m4_tu(vuint16m4_t maskedoff, uint16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m8_t test_vmv_v_v_u16m8_tu(vuint16m8_t maskedoff, vuint16m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m8_t test_vmv_v_x_u16m8_tu(vuint16m8_t maskedoff, uint16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32mf2_t test_vmv_v_v_u32mf2_tu(vuint32mf2_t maskedoff, vuint32mf2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32mf2_t test_vmv_v_x_u32mf2_tu(vuint32mf2_t maskedoff, uint32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m1_t test_vmv_v_v_u32m1_tu(vuint32m1_t maskedoff, vuint32m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m1_t test_vmv_v_x_u32m1_tu(vuint32m1_t maskedoff, uint32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m2_t test_vmv_v_v_u32m2_tu(vuint32m2_t maskedoff, vuint32m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m2_t test_vmv_v_x_u32m2_tu(vuint32m2_t maskedoff, uint32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m4_t test_vmv_v_v_u32m4_tu(vuint32m4_t maskedoff, vuint32m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m4_t test_vmv_v_x_u32m4_tu(vuint32m4_t maskedoff, uint32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m8_t test_vmv_v_v_u32m8_tu(vuint32m8_t maskedoff, vuint32m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m8_t test_vmv_v_x_u32m8_tu(vuint32m8_t maskedoff, uint32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m1_t test_vmv_v_v_u64m1_tu(vuint64m1_t maskedoff, vuint64m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m1_t test_vmv_v_x_u64m1_tu(vuint64m1_t maskedoff, uint64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m2_t test_vmv_v_v_u64m2_tu(vuint64m2_t maskedoff, vuint64m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m2_t test_vmv_v_x_u64m2_tu(vuint64m2_t maskedoff, uint64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m4_t test_vmv_v_v_u64m4_tu(vuint64m4_t maskedoff, vuint64m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m4_t test_vmv_v_x_u64m4_tu(vuint64m4_t maskedoff, uint64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m8_t test_vmv_v_v_u64m8_tu(vuint64m8_t maskedoff, vuint64m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m8_t test_vmv_v_x_u64m8_tu(vuint64m8_t maskedoff, uint64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat32mf2_t test_vmv_v_v_f32mf2_tu(vfloat32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat32m1_t test_vmv_v_v_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat32m2_t test_vmv_v_v_f32m2_tu(vfloat32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat32m4_t test_vmv_v_v_f32m4_tu(vfloat32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat32m8_t test_vmv_v_v_f32m8_tu(vfloat32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat64m1_t test_vmv_v_v_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat64m2_t test_vmv_v_v_f64m2_tu(vfloat64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat64m4_t test_vmv_v_v_f64m4_tu(vfloat64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat64m8_t test_vmv_v_v_f64m8_tu(vfloat64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_tu-1.C
new file mode 100644
index 00000000000..fcda5352b63
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_tu-1.C
@@ -0,0 +1,392 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test_vmv_v_v_i8mf8_tu(vint8mf8_t maskedoff, vint8mf8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8mf8_t test_vmv_v_x_i8mf8_tu(vint8mf8_t maskedoff, int8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8mf4_t test_vmv_v_v_i8mf4_tu(vint8mf4_t maskedoff, vint8mf4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8mf4_t test_vmv_v_x_i8mf4_tu(vint8mf4_t maskedoff, int8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8mf2_t test_vmv_v_v_i8mf2_tu(vint8mf2_t maskedoff, vint8mf2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8mf2_t test_vmv_v_x_i8mf2_tu(vint8mf2_t maskedoff, int8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m1_t test_vmv_v_v_i8m1_tu(vint8m1_t maskedoff, vint8m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m1_t test_vmv_v_x_i8m1_tu(vint8m1_t maskedoff, int8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m2_t test_vmv_v_v_i8m2_tu(vint8m2_t maskedoff, vint8m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m2_t test_vmv_v_x_i8m2_tu(vint8m2_t maskedoff, int8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m4_t test_vmv_v_v_i8m4_tu(vint8m4_t maskedoff, vint8m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m4_t test_vmv_v_x_i8m4_tu(vint8m4_t maskedoff, int8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m8_t test_vmv_v_v_i8m8_tu(vint8m8_t maskedoff, vint8m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint8m8_t test_vmv_v_x_i8m8_tu(vint8m8_t maskedoff, int8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16mf4_t test_vmv_v_v_i16mf4_tu(vint16mf4_t maskedoff, vint16mf4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16mf4_t test_vmv_v_x_i16mf4_tu(vint16mf4_t maskedoff, int16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16mf2_t test_vmv_v_v_i16mf2_tu(vint16mf2_t maskedoff, vint16mf2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16mf2_t test_vmv_v_x_i16mf2_tu(vint16mf2_t maskedoff, int16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m1_t test_vmv_v_v_i16m1_tu(vint16m1_t maskedoff, vint16m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m1_t test_vmv_v_x_i16m1_tu(vint16m1_t maskedoff, int16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m2_t test_vmv_v_v_i16m2_tu(vint16m2_t maskedoff, vint16m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m2_t test_vmv_v_x_i16m2_tu(vint16m2_t maskedoff, int16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m4_t test_vmv_v_v_i16m4_tu(vint16m4_t maskedoff, vint16m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m4_t test_vmv_v_x_i16m4_tu(vint16m4_t maskedoff, int16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m8_t test_vmv_v_v_i16m8_tu(vint16m8_t maskedoff, vint16m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint16m8_t test_vmv_v_x_i16m8_tu(vint16m8_t maskedoff, int16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32mf2_t test_vmv_v_v_i32mf2_tu(vint32mf2_t maskedoff, vint32mf2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32mf2_t test_vmv_v_x_i32mf2_tu(vint32mf2_t maskedoff, int32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m1_t test_vmv_v_v_i32m1_tu(vint32m1_t maskedoff, vint32m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m1_t test_vmv_v_x_i32m1_tu(vint32m1_t maskedoff, int32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m2_t test_vmv_v_v_i32m2_tu(vint32m2_t maskedoff, vint32m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m2_t test_vmv_v_x_i32m2_tu(vint32m2_t maskedoff, int32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m4_t test_vmv_v_v_i32m4_tu(vint32m4_t maskedoff, vint32m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m4_t test_vmv_v_x_i32m4_tu(vint32m4_t maskedoff, int32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m8_t test_vmv_v_v_i32m8_tu(vint32m8_t maskedoff, vint32m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint32m8_t test_vmv_v_x_i32m8_tu(vint32m8_t maskedoff, int32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m1_t test_vmv_v_v_i64m1_tu(vint64m1_t maskedoff, vint64m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m1_t test_vmv_v_x_i64m1_tu(vint64m1_t maskedoff, int64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m2_t test_vmv_v_v_i64m2_tu(vint64m2_t maskedoff, vint64m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m2_t test_vmv_v_x_i64m2_tu(vint64m2_t maskedoff, int64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m4_t test_vmv_v_v_i64m4_tu(vint64m4_t maskedoff, vint64m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m4_t test_vmv_v_x_i64m4_tu(vint64m4_t maskedoff, int64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m8_t test_vmv_v_v_i64m8_tu(vint64m8_t maskedoff, vint64m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vint64m8_t test_vmv_v_x_i64m8_tu(vint64m8_t maskedoff, int64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8mf8_t test_vmv_v_v_u8mf8_tu(vuint8mf8_t maskedoff, vuint8mf8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8mf8_t test_vmv_v_x_u8mf8_tu(vuint8mf8_t maskedoff, uint8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8mf4_t test_vmv_v_v_u8mf4_tu(vuint8mf4_t maskedoff, vuint8mf4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8mf4_t test_vmv_v_x_u8mf4_tu(vuint8mf4_t maskedoff, uint8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8mf2_t test_vmv_v_v_u8mf2_tu(vuint8mf2_t maskedoff, vuint8mf2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8mf2_t test_vmv_v_x_u8mf2_tu(vuint8mf2_t maskedoff, uint8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m1_t test_vmv_v_v_u8m1_tu(vuint8m1_t maskedoff, vuint8m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m1_t test_vmv_v_x_u8m1_tu(vuint8m1_t maskedoff, uint8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m2_t test_vmv_v_v_u8m2_tu(vuint8m2_t maskedoff, vuint8m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m2_t test_vmv_v_x_u8m2_tu(vuint8m2_t maskedoff, uint8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m4_t test_vmv_v_v_u8m4_tu(vuint8m4_t maskedoff, vuint8m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m4_t test_vmv_v_x_u8m4_tu(vuint8m4_t maskedoff, uint8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m8_t test_vmv_v_v_u8m8_tu(vuint8m8_t maskedoff, vuint8m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint8m8_t test_vmv_v_x_u8m8_tu(vuint8m8_t maskedoff, uint8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16mf4_t test_vmv_v_v_u16mf4_tu(vuint16mf4_t maskedoff, vuint16mf4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16mf4_t test_vmv_v_x_u16mf4_tu(vuint16mf4_t maskedoff, uint16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16mf2_t test_vmv_v_v_u16mf2_tu(vuint16mf2_t maskedoff, vuint16mf2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16mf2_t test_vmv_v_x_u16mf2_tu(vuint16mf2_t maskedoff, uint16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m1_t test_vmv_v_v_u16m1_tu(vuint16m1_t maskedoff, vuint16m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m1_t test_vmv_v_x_u16m1_tu(vuint16m1_t maskedoff, uint16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m2_t test_vmv_v_v_u16m2_tu(vuint16m2_t maskedoff, vuint16m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m2_t test_vmv_v_x_u16m2_tu(vuint16m2_t maskedoff, uint16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m4_t test_vmv_v_v_u16m4_tu(vuint16m4_t maskedoff, vuint16m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m4_t test_vmv_v_x_u16m4_tu(vuint16m4_t maskedoff, uint16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m8_t test_vmv_v_v_u16m8_tu(vuint16m8_t maskedoff, vuint16m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint16m8_t test_vmv_v_x_u16m8_tu(vuint16m8_t maskedoff, uint16_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32mf2_t test_vmv_v_v_u32mf2_tu(vuint32mf2_t maskedoff, vuint32mf2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32mf2_t test_vmv_v_x_u32mf2_tu(vuint32mf2_t maskedoff, uint32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m1_t test_vmv_v_v_u32m1_tu(vuint32m1_t maskedoff, vuint32m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m1_t test_vmv_v_x_u32m1_tu(vuint32m1_t maskedoff, uint32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m2_t test_vmv_v_v_u32m2_tu(vuint32m2_t maskedoff, vuint32m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m2_t test_vmv_v_x_u32m2_tu(vuint32m2_t maskedoff, uint32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m4_t test_vmv_v_v_u32m4_tu(vuint32m4_t maskedoff, vuint32m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m4_t test_vmv_v_x_u32m4_tu(vuint32m4_t maskedoff, uint32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m8_t test_vmv_v_v_u32m8_tu(vuint32m8_t maskedoff, vuint32m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint32m8_t test_vmv_v_x_u32m8_tu(vuint32m8_t maskedoff, uint32_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m1_t test_vmv_v_v_u64m1_tu(vuint64m1_t maskedoff, vuint64m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m1_t test_vmv_v_x_u64m1_tu(vuint64m1_t maskedoff, uint64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m2_t test_vmv_v_v_u64m2_tu(vuint64m2_t maskedoff, vuint64m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m2_t test_vmv_v_x_u64m2_tu(vuint64m2_t maskedoff, uint64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m4_t test_vmv_v_v_u64m4_tu(vuint64m4_t maskedoff, vuint64m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m4_t test_vmv_v_x_u64m4_tu(vuint64m4_t maskedoff, uint64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m8_t test_vmv_v_v_u64m8_tu(vuint64m8_t maskedoff, vuint64m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vuint64m8_t test_vmv_v_x_u64m8_tu(vuint64m8_t maskedoff, uint64_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat32mf2_t test_vmv_v_v_f32mf2_tu(vfloat32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat32m1_t test_vmv_v_v_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat32m2_t test_vmv_v_v_f32m2_tu(vfloat32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat32m4_t test_vmv_v_v_f32m4_tu(vfloat32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat32m8_t test_vmv_v_v_f32m8_tu(vfloat32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat64m1_t test_vmv_v_v_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat64m2_t test_vmv_v_v_f64m2_tu(vfloat64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat64m4_t test_vmv_v_v_f64m4_tu(vfloat64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
+
+vfloat64m8_t test_vmv_v_v_f64m8_tu(vfloat64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
+  return __riscv_vmv_v_tu(maskedoff, src, vl);
+}
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-1.C
new file mode 100644
index 00000000000..ce582491948
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-1.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmv_v_x_i8mf8(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf8(src,vl);
+}
+
+
+vint8mf4_t test___riscv_vmv_v_x_i8mf4(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf4(src,vl);
+}
+
+
+vint8mf2_t test___riscv_vmv_v_x_i8mf2(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf2(src,vl);
+}
+
+
+vint8m1_t test___riscv_vmv_v_x_i8m1(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m1(src,vl);
+}
+
+
+vint8m2_t test___riscv_vmv_v_x_i8m2(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m2(src,vl);
+}
+
+
+vint8m4_t test___riscv_vmv_v_x_i8m4(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m4(src,vl);
+}
+
+
+vint8m8_t test___riscv_vmv_v_x_i8m8(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m8(src,vl);
+}
+
+
+vint16mf4_t test___riscv_vmv_v_x_i16mf4(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16mf4(src,vl);
+}
+
+
+vint16mf2_t test___riscv_vmv_v_x_i16mf2(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16mf2(src,vl);
+}
+
+
+vint16m1_t test___riscv_vmv_v_x_i16m1(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m1(src,vl);
+}
+
+
+vint16m2_t test___riscv_vmv_v_x_i16m2(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m2(src,vl);
+}
+
+
+vint16m4_t test___riscv_vmv_v_x_i16m4(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m4(src,vl);
+}
+
+
+vint16m8_t test___riscv_vmv_v_x_i16m8(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m8(src,vl);
+}
+
+
+vint32mf2_t test___riscv_vmv_v_x_i32mf2(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32mf2(src,vl);
+}
+
+
+vint32m1_t test___riscv_vmv_v_x_i32m1(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m1(src,vl);
+}
+
+
+vint32m2_t test___riscv_vmv_v_x_i32m2(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m2(src,vl);
+}
+
+
+vint32m4_t test___riscv_vmv_v_x_i32m4(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m4(src,vl);
+}
+
+
+vint32m8_t test___riscv_vmv_v_x_i32m8(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m8(src,vl);
+}
+
+
+vint64m1_t test___riscv_vmv_v_x_i64m1(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m1(src,vl);
+}
+
+
+vint64m2_t test___riscv_vmv_v_x_i64m2(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m2(src,vl);
+}
+
+
+vint64m4_t test___riscv_vmv_v_x_i64m4(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m4(src,vl);
+}
+
+
+vint64m8_t test___riscv_vmv_v_x_i64m8(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m8(src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmv_v_x_u8mf8(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf8(src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmv_v_x_u8mf4(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf4(src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmv_v_x_u8mf2(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf2(src,vl);
+}
+
+
+vuint8m1_t test___riscv_vmv_v_x_u8m1(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m1(src,vl);
+}
+
+
+vuint8m2_t test___riscv_vmv_v_x_u8m2(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m2(src,vl);
+}
+
+
+vuint8m4_t test___riscv_vmv_v_x_u8m4(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m4(src,vl);
+}
+
+
+vuint8m8_t test___riscv_vmv_v_x_u8m8(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m8(src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmv_v_x_u16mf4(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16mf4(src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmv_v_x_u16mf2(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16mf2(src,vl);
+}
+
+
+vuint16m1_t test___riscv_vmv_v_x_u16m1(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m1(src,vl);
+}
+
+
+vuint16m2_t test___riscv_vmv_v_x_u16m2(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m2(src,vl);
+}
+
+
+vuint16m4_t test___riscv_vmv_v_x_u16m4(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m4(src,vl);
+}
+
+
+vuint16m8_t test___riscv_vmv_v_x_u16m8(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m8(src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmv_v_x_u32mf2(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32mf2(src,vl);
+}
+
+
+vuint32m1_t test___riscv_vmv_v_x_u32m1(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m1(src,vl);
+}
+
+
+vuint32m2_t test___riscv_vmv_v_x_u32m2(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m2(src,vl);
+}
+
+
+vuint32m4_t test___riscv_vmv_v_x_u32m4(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m4(src,vl);
+}
+
+
+vuint32m8_t test___riscv_vmv_v_x_u32m8(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m8(src,vl);
+}
+
+
+vuint64m1_t test___riscv_vmv_v_x_u64m1(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m1(src,vl);
+}
+
+
+vuint64m2_t test___riscv_vmv_v_x_u64m2(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m2(src,vl);
+}
+
+
+vuint64m4_t test___riscv_vmv_v_x_u64m4(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m4(src,vl);
+}
+
+
+vuint64m8_t test___riscv_vmv_v_x_u64m8(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m8(src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vlse} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-2.C
new file mode 100644
index 00000000000..36b017be04d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-2.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmv_v_x_i8mf8(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf8(src,31);
+}
+
+
+vint8mf4_t test___riscv_vmv_v_x_i8mf4(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf4(src,31);
+}
+
+
+vint8mf2_t test___riscv_vmv_v_x_i8mf2(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf2(src,31);
+}
+
+
+vint8m1_t test___riscv_vmv_v_x_i8m1(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m1(src,31);
+}
+
+
+vint8m2_t test___riscv_vmv_v_x_i8m2(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m2(src,31);
+}
+
+
+vint8m4_t test___riscv_vmv_v_x_i8m4(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m4(src,31);
+}
+
+
+vint8m8_t test___riscv_vmv_v_x_i8m8(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m8(src,31);
+}
+
+
+vint16mf4_t test___riscv_vmv_v_x_i16mf4(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16mf4(src,31);
+}
+
+
+vint16mf2_t test___riscv_vmv_v_x_i16mf2(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16mf2(src,31);
+}
+
+
+vint16m1_t test___riscv_vmv_v_x_i16m1(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m1(src,31);
+}
+
+
+vint16m2_t test___riscv_vmv_v_x_i16m2(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m2(src,31);
+}
+
+
+vint16m4_t test___riscv_vmv_v_x_i16m4(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m4(src,31);
+}
+
+
+vint16m8_t test___riscv_vmv_v_x_i16m8(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m8(src,31);
+}
+
+
+vint32mf2_t test___riscv_vmv_v_x_i32mf2(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32mf2(src,31);
+}
+
+
+vint32m1_t test___riscv_vmv_v_x_i32m1(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m1(src,31);
+}
+
+
+vint32m2_t test___riscv_vmv_v_x_i32m2(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m2(src,31);
+}
+
+
+vint32m4_t test___riscv_vmv_v_x_i32m4(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m4(src,31);
+}
+
+
+vint32m8_t test___riscv_vmv_v_x_i32m8(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m8(src,31);
+}
+
+
+vint64m1_t test___riscv_vmv_v_x_i64m1(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m1(src,31);
+}
+
+
+vint64m2_t test___riscv_vmv_v_x_i64m2(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m2(src,31);
+}
+
+
+vint64m4_t test___riscv_vmv_v_x_i64m4(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m4(src,31);
+}
+
+
+vint64m8_t test___riscv_vmv_v_x_i64m8(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m8(src,31);
+}
+
+
+vuint8mf8_t test___riscv_vmv_v_x_u8mf8(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf8(src,31);
+}
+
+
+vuint8mf4_t test___riscv_vmv_v_x_u8mf4(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf4(src,31);
+}
+
+
+vuint8mf2_t test___riscv_vmv_v_x_u8mf2(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf2(src,31);
+}
+
+
+vuint8m1_t test___riscv_vmv_v_x_u8m1(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m1(src,31);
+}
+
+
+vuint8m2_t test___riscv_vmv_v_x_u8m2(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m2(src,31);
+}
+
+
+vuint8m4_t test___riscv_vmv_v_x_u8m4(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m4(src,31);
+}
+
+
+vuint8m8_t test___riscv_vmv_v_x_u8m8(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m8(src,31);
+}
+
+
+vuint16mf4_t test___riscv_vmv_v_x_u16mf4(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16mf4(src,31);
+}
+
+
+vuint16mf2_t test___riscv_vmv_v_x_u16mf2(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16mf2(src,31);
+}
+
+
+vuint16m1_t test___riscv_vmv_v_x_u16m1(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m1(src,31);
+}
+
+
+vuint16m2_t test___riscv_vmv_v_x_u16m2(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m2(src,31);
+}
+
+
+vuint16m4_t test___riscv_vmv_v_x_u16m4(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m4(src,31);
+}
+
+
+vuint16m8_t test___riscv_vmv_v_x_u16m8(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m8(src,31);
+}
+
+
+vuint32mf2_t test___riscv_vmv_v_x_u32mf2(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32mf2(src,31);
+}
+
+
+vuint32m1_t test___riscv_vmv_v_x_u32m1(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m1(src,31);
+}
+
+
+vuint32m2_t test___riscv_vmv_v_x_u32m2(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m2(src,31);
+}
+
+
+vuint32m4_t test___riscv_vmv_v_x_u32m4(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m4(src,31);
+}
+
+
+vuint32m8_t test___riscv_vmv_v_x_u32m8(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m8(src,31);
+}
+
+
+vuint64m1_t test___riscv_vmv_v_x_u64m1(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m1(src,31);
+}
+
+
+vuint64m2_t test___riscv_vmv_v_x_u64m2(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m2(src,31);
+}
+
+
+vuint64m4_t test___riscv_vmv_v_x_u64m4(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m4(src,31);
+}
+
+
+vuint64m8_t test___riscv_vmv_v_x_u64m8(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m8(src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vlse} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-3.C
new file mode 100644
index 00000000000..aa3d76fd3bd
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-3.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmv_v_x_i8mf8(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf8(src,32);
+}
+
+
+vint8mf4_t test___riscv_vmv_v_x_i8mf4(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf4(src,32);
+}
+
+
+vint8mf2_t test___riscv_vmv_v_x_i8mf2(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf2(src,32);
+}
+
+
+vint8m1_t test___riscv_vmv_v_x_i8m1(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m1(src,32);
+}
+
+
+vint8m2_t test___riscv_vmv_v_x_i8m2(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m2(src,32);
+}
+
+
+vint8m4_t test___riscv_vmv_v_x_i8m4(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m4(src,32);
+}
+
+
+vint8m8_t test___riscv_vmv_v_x_i8m8(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m8(src,32);
+}
+
+
+vint16mf4_t test___riscv_vmv_v_x_i16mf4(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16mf4(src,32);
+}
+
+
+vint16mf2_t test___riscv_vmv_v_x_i16mf2(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16mf2(src,32);
+}
+
+
+vint16m1_t test___riscv_vmv_v_x_i16m1(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m1(src,32);
+}
+
+
+vint16m2_t test___riscv_vmv_v_x_i16m2(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m2(src,32);
+}
+
+
+vint16m4_t test___riscv_vmv_v_x_i16m4(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m4(src,32);
+}
+
+
+vint16m8_t test___riscv_vmv_v_x_i16m8(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m8(src,32);
+}
+
+
+vint32mf2_t test___riscv_vmv_v_x_i32mf2(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32mf2(src,32);
+}
+
+
+vint32m1_t test___riscv_vmv_v_x_i32m1(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m1(src,32);
+}
+
+
+vint32m2_t test___riscv_vmv_v_x_i32m2(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m2(src,32);
+}
+
+
+vint32m4_t test___riscv_vmv_v_x_i32m4(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m4(src,32);
+}
+
+
+vint32m8_t test___riscv_vmv_v_x_i32m8(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m8(src,32);
+}
+
+
+vint64m1_t test___riscv_vmv_v_x_i64m1(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m1(src,32);
+}
+
+
+vint64m2_t test___riscv_vmv_v_x_i64m2(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m2(src,32);
+}
+
+
+vint64m4_t test___riscv_vmv_v_x_i64m4(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m4(src,32);
+}
+
+
+vint64m8_t test___riscv_vmv_v_x_i64m8(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m8(src,32);
+}
+
+
+vuint8mf8_t test___riscv_vmv_v_x_u8mf8(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf8(src,32);
+}
+
+
+vuint8mf4_t test___riscv_vmv_v_x_u8mf4(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf4(src,32);
+}
+
+
+vuint8mf2_t test___riscv_vmv_v_x_u8mf2(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf2(src,32);
+}
+
+
+vuint8m1_t test___riscv_vmv_v_x_u8m1(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m1(src,32);
+}
+
+
+vuint8m2_t test___riscv_vmv_v_x_u8m2(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m2(src,32);
+}
+
+
+vuint8m4_t test___riscv_vmv_v_x_u8m4(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m4(src,32);
+}
+
+
+vuint8m8_t test___riscv_vmv_v_x_u8m8(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m8(src,32);
+}
+
+
+vuint16mf4_t test___riscv_vmv_v_x_u16mf4(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16mf4(src,32);
+}
+
+
+vuint16mf2_t test___riscv_vmv_v_x_u16mf2(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16mf2(src,32);
+}
+
+
+vuint16m1_t test___riscv_vmv_v_x_u16m1(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m1(src,32);
+}
+
+
+vuint16m2_t test___riscv_vmv_v_x_u16m2(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m2(src,32);
+}
+
+
+vuint16m4_t test___riscv_vmv_v_x_u16m4(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m4(src,32);
+}
+
+
+vuint16m8_t test___riscv_vmv_v_x_u16m8(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m8(src,32);
+}
+
+
+vuint32mf2_t test___riscv_vmv_v_x_u32mf2(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32mf2(src,32);
+}
+
+
+vuint32m1_t test___riscv_vmv_v_x_u32m1(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m1(src,32);
+}
+
+
+vuint32m2_t test___riscv_vmv_v_x_u32m2(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m2(src,32);
+}
+
+
+vuint32m4_t test___riscv_vmv_v_x_u32m4(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m4(src,32);
+}
+
+
+vuint32m8_t test___riscv_vmv_v_x_u32m8(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m8(src,32);
+}
+
+
+vuint64m1_t test___riscv_vmv_v_x_u64m1(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m1(src,32);
+}
+
+
+vuint64m2_t test___riscv_vmv_v_x_u64m2(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m2(src,32);
+}
+
+
+vuint64m4_t test___riscv_vmv_v_x_u64m4(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m4(src,32);
+}
+
+
+vuint64m8_t test___riscv_vmv_v_x_u64m8(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m8(src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vlse} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-1.C
new file mode 100644
index 00000000000..bbfe50de52b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-1.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmv_v_x_i8mf8(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf8(src,vl);
+}
+
+
+vint8mf4_t test___riscv_vmv_v_x_i8mf4(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf4(src,vl);
+}
+
+
+vint8mf2_t test___riscv_vmv_v_x_i8mf2(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf2(src,vl);
+}
+
+
+vint8m1_t test___riscv_vmv_v_x_i8m1(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m1(src,vl);
+}
+
+
+vint8m2_t test___riscv_vmv_v_x_i8m2(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m2(src,vl);
+}
+
+
+vint8m4_t test___riscv_vmv_v_x_i8m4(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m4(src,vl);
+}
+
+
+vint8m8_t test___riscv_vmv_v_x_i8m8(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m8(src,vl);
+}
+
+
+vint16mf4_t test___riscv_vmv_v_x_i16mf4(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16mf4(src,vl);
+}
+
+
+vint16mf2_t test___riscv_vmv_v_x_i16mf2(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16mf2(src,vl);
+}
+
+
+vint16m1_t test___riscv_vmv_v_x_i16m1(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m1(src,vl);
+}
+
+
+vint16m2_t test___riscv_vmv_v_x_i16m2(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m2(src,vl);
+}
+
+
+vint16m4_t test___riscv_vmv_v_x_i16m4(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m4(src,vl);
+}
+
+
+vint16m8_t test___riscv_vmv_v_x_i16m8(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m8(src,vl);
+}
+
+
+vint32mf2_t test___riscv_vmv_v_x_i32mf2(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32mf2(src,vl);
+}
+
+
+vint32m1_t test___riscv_vmv_v_x_i32m1(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m1(src,vl);
+}
+
+
+vint32m2_t test___riscv_vmv_v_x_i32m2(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m2(src,vl);
+}
+
+
+vint32m4_t test___riscv_vmv_v_x_i32m4(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m4(src,vl);
+}
+
+
+vint32m8_t test___riscv_vmv_v_x_i32m8(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m8(src,vl);
+}
+
+
+vint64m1_t test___riscv_vmv_v_x_i64m1(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m1(src,vl);
+}
+
+
+vint64m2_t test___riscv_vmv_v_x_i64m2(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m2(src,vl);
+}
+
+
+vint64m4_t test___riscv_vmv_v_x_i64m4(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m4(src,vl);
+}
+
+
+vint64m8_t test___riscv_vmv_v_x_i64m8(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m8(src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmv_v_x_u8mf8(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf8(src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmv_v_x_u8mf4(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf4(src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmv_v_x_u8mf2(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf2(src,vl);
+}
+
+
+vuint8m1_t test___riscv_vmv_v_x_u8m1(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m1(src,vl);
+}
+
+
+vuint8m2_t test___riscv_vmv_v_x_u8m2(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m2(src,vl);
+}
+
+
+vuint8m4_t test___riscv_vmv_v_x_u8m4(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m4(src,vl);
+}
+
+
+vuint8m8_t test___riscv_vmv_v_x_u8m8(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m8(src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmv_v_x_u16mf4(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16mf4(src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmv_v_x_u16mf2(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16mf2(src,vl);
+}
+
+
+vuint16m1_t test___riscv_vmv_v_x_u16m1(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m1(src,vl);
+}
+
+
+vuint16m2_t test___riscv_vmv_v_x_u16m2(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m2(src,vl);
+}
+
+
+vuint16m4_t test___riscv_vmv_v_x_u16m4(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m4(src,vl);
+}
+
+
+vuint16m8_t test___riscv_vmv_v_x_u16m8(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m8(src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmv_v_x_u32mf2(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32mf2(src,vl);
+}
+
+
+vuint32m1_t test___riscv_vmv_v_x_u32m1(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m1(src,vl);
+}
+
+
+vuint32m2_t test___riscv_vmv_v_x_u32m2(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m2(src,vl);
+}
+
+
+vuint32m4_t test___riscv_vmv_v_x_u32m4(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m4(src,vl);
+}
+
+
+vuint32m8_t test___riscv_vmv_v_x_u32m8(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m8(src,vl);
+}
+
+
+vuint64m1_t test___riscv_vmv_v_x_u64m1(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m1(src,vl);
+}
+
+
+vuint64m2_t test___riscv_vmv_v_x_u64m2(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m2(src,vl);
+}
+
+
+vuint64m4_t test___riscv_vmv_v_x_u64m4(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m4(src,vl);
+}
+
+
+vuint64m8_t test___riscv_vmv_v_x_u64m8(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m8(src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-2.C
new file mode 100644
index 00000000000..1fd2084dfc8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-2.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmv_v_x_i8mf8(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf8(src,31);
+}
+
+
+vint8mf4_t test___riscv_vmv_v_x_i8mf4(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf4(src,31);
+}
+
+
+vint8mf2_t test___riscv_vmv_v_x_i8mf2(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf2(src,31);
+}
+
+
+vint8m1_t test___riscv_vmv_v_x_i8m1(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m1(src,31);
+}
+
+
+vint8m2_t test___riscv_vmv_v_x_i8m2(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m2(src,31);
+}
+
+
+vint8m4_t test___riscv_vmv_v_x_i8m4(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m4(src,31);
+}
+
+
+vint8m8_t test___riscv_vmv_v_x_i8m8(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m8(src,31);
+}
+
+
+vint16mf4_t test___riscv_vmv_v_x_i16mf4(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16mf4(src,31);
+}
+
+
+vint16mf2_t test___riscv_vmv_v_x_i16mf2(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16mf2(src,31);
+}
+
+
+vint16m1_t test___riscv_vmv_v_x_i16m1(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m1(src,31);
+}
+
+
+vint16m2_t test___riscv_vmv_v_x_i16m2(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m2(src,31);
+}
+
+
+vint16m4_t test___riscv_vmv_v_x_i16m4(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m4(src,31);
+}
+
+
+vint16m8_t test___riscv_vmv_v_x_i16m8(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m8(src,31);
+}
+
+
+vint32mf2_t test___riscv_vmv_v_x_i32mf2(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32mf2(src,31);
+}
+
+
+vint32m1_t test___riscv_vmv_v_x_i32m1(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m1(src,31);
+}
+
+
+vint32m2_t test___riscv_vmv_v_x_i32m2(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m2(src,31);
+}
+
+
+vint32m4_t test___riscv_vmv_v_x_i32m4(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m4(src,31);
+}
+
+
+vint32m8_t test___riscv_vmv_v_x_i32m8(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m8(src,31);
+}
+
+
+vint64m1_t test___riscv_vmv_v_x_i64m1(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m1(src,31);
+}
+
+
+vint64m2_t test___riscv_vmv_v_x_i64m2(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m2(src,31);
+}
+
+
+vint64m4_t test___riscv_vmv_v_x_i64m4(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m4(src,31);
+}
+
+
+vint64m8_t test___riscv_vmv_v_x_i64m8(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m8(src,31);
+}
+
+
+vuint8mf8_t test___riscv_vmv_v_x_u8mf8(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf8(src,31);
+}
+
+
+vuint8mf4_t test___riscv_vmv_v_x_u8mf4(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf4(src,31);
+}
+
+
+vuint8mf2_t test___riscv_vmv_v_x_u8mf2(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf2(src,31);
+}
+
+
+vuint8m1_t test___riscv_vmv_v_x_u8m1(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m1(src,31);
+}
+
+
+vuint8m2_t test___riscv_vmv_v_x_u8m2(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m2(src,31);
+}
+
+
+vuint8m4_t test___riscv_vmv_v_x_u8m4(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m4(src,31);
+}
+
+
+vuint8m8_t test___riscv_vmv_v_x_u8m8(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m8(src,31);
+}
+
+
+vuint16mf4_t test___riscv_vmv_v_x_u16mf4(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16mf4(src,31);
+}
+
+
+vuint16mf2_t test___riscv_vmv_v_x_u16mf2(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16mf2(src,31);
+}
+
+
+vuint16m1_t test___riscv_vmv_v_x_u16m1(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m1(src,31);
+}
+
+
+vuint16m2_t test___riscv_vmv_v_x_u16m2(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m2(src,31);
+}
+
+
+vuint16m4_t test___riscv_vmv_v_x_u16m4(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m4(src,31);
+}
+
+
+vuint16m8_t test___riscv_vmv_v_x_u16m8(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m8(src,31);
+}
+
+
+vuint32mf2_t test___riscv_vmv_v_x_u32mf2(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32mf2(src,31);
+}
+
+
+vuint32m1_t test___riscv_vmv_v_x_u32m1(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m1(src,31);
+}
+
+
+vuint32m2_t test___riscv_vmv_v_x_u32m2(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m2(src,31);
+}
+
+
+vuint32m4_t test___riscv_vmv_v_x_u32m4(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m4(src,31);
+}
+
+
+vuint32m8_t test___riscv_vmv_v_x_u32m8(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m8(src,31);
+}
+
+
+vuint64m1_t test___riscv_vmv_v_x_u64m1(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m1(src,31);
+}
+
+
+vuint64m2_t test___riscv_vmv_v_x_u64m2(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m2(src,31);
+}
+
+
+vuint64m4_t test___riscv_vmv_v_x_u64m4(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m4(src,31);
+}
+
+
+vuint64m8_t test___riscv_vmv_v_x_u64m8(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m8(src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-3.C
new file mode 100644
index 00000000000..cc68b2936e1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-3.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmv_v_x_i8mf8(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf8(src,32);
+}
+
+
+vint8mf4_t test___riscv_vmv_v_x_i8mf4(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf4(src,32);
+}
+
+
+vint8mf2_t test___riscv_vmv_v_x_i8mf2(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8mf2(src,32);
+}
+
+
+vint8m1_t test___riscv_vmv_v_x_i8m1(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m1(src,32);
+}
+
+
+vint8m2_t test___riscv_vmv_v_x_i8m2(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m2(src,32);
+}
+
+
+vint8m4_t test___riscv_vmv_v_x_i8m4(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m4(src,32);
+}
+
+
+vint8m8_t test___riscv_vmv_v_x_i8m8(int8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i8m8(src,32);
+}
+
+
+vint16mf4_t test___riscv_vmv_v_x_i16mf4(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16mf4(src,32);
+}
+
+
+vint16mf2_t test___riscv_vmv_v_x_i16mf2(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16mf2(src,32);
+}
+
+
+vint16m1_t test___riscv_vmv_v_x_i16m1(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m1(src,32);
+}
+
+
+vint16m2_t test___riscv_vmv_v_x_i16m2(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m2(src,32);
+}
+
+
+vint16m4_t test___riscv_vmv_v_x_i16m4(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m4(src,32);
+}
+
+
+vint16m8_t test___riscv_vmv_v_x_i16m8(int16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i16m8(src,32);
+}
+
+
+vint32mf2_t test___riscv_vmv_v_x_i32mf2(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32mf2(src,32);
+}
+
+
+vint32m1_t test___riscv_vmv_v_x_i32m1(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m1(src,32);
+}
+
+
+vint32m2_t test___riscv_vmv_v_x_i32m2(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m2(src,32);
+}
+
+
+vint32m4_t test___riscv_vmv_v_x_i32m4(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m4(src,32);
+}
+
+
+vint32m8_t test___riscv_vmv_v_x_i32m8(int32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i32m8(src,32);
+}
+
+
+vint64m1_t test___riscv_vmv_v_x_i64m1(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m1(src,32);
+}
+
+
+vint64m2_t test___riscv_vmv_v_x_i64m2(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m2(src,32);
+}
+
+
+vint64m4_t test___riscv_vmv_v_x_i64m4(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m4(src,32);
+}
+
+
+vint64m8_t test___riscv_vmv_v_x_i64m8(int64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_i64m8(src,32);
+}
+
+
+vuint8mf8_t test___riscv_vmv_v_x_u8mf8(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf8(src,32);
+}
+
+
+vuint8mf4_t test___riscv_vmv_v_x_u8mf4(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf4(src,32);
+}
+
+
+vuint8mf2_t test___riscv_vmv_v_x_u8mf2(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8mf2(src,32);
+}
+
+
+vuint8m1_t test___riscv_vmv_v_x_u8m1(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m1(src,32);
+}
+
+
+vuint8m2_t test___riscv_vmv_v_x_u8m2(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m2(src,32);
+}
+
+
+vuint8m4_t test___riscv_vmv_v_x_u8m4(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m4(src,32);
+}
+
+
+vuint8m8_t test___riscv_vmv_v_x_u8m8(uint8_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u8m8(src,32);
+}
+
+
+vuint16mf4_t test___riscv_vmv_v_x_u16mf4(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16mf4(src,32);
+}
+
+
+vuint16mf2_t test___riscv_vmv_v_x_u16mf2(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16mf2(src,32);
+}
+
+
+vuint16m1_t test___riscv_vmv_v_x_u16m1(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m1(src,32);
+}
+
+
+vuint16m2_t test___riscv_vmv_v_x_u16m2(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m2(src,32);
+}
+
+
+vuint16m4_t test___riscv_vmv_v_x_u16m4(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m4(src,32);
+}
+
+
+vuint16m8_t test___riscv_vmv_v_x_u16m8(uint16_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u16m8(src,32);
+}
+
+
+vuint32mf2_t test___riscv_vmv_v_x_u32mf2(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32mf2(src,32);
+}
+
+
+vuint32m1_t test___riscv_vmv_v_x_u32m1(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m1(src,32);
+}
+
+
+vuint32m2_t test___riscv_vmv_v_x_u32m2(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m2(src,32);
+}
+
+
+vuint32m4_t test___riscv_vmv_v_x_u32m4(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m4(src,32);
+}
+
+
+vuint32m8_t test___riscv_vmv_v_x_u32m8(uint32_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u32m8(src,32);
+}
+
+
+vuint64m1_t test___riscv_vmv_v_x_u64m1(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m1(src,32);
+}
+
+
+vuint64m2_t test___riscv_vmv_v_x_u64m2(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m2(src,32);
+}
+
+
+vuint64m4_t test___riscv_vmv_v_x_u64m4(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m4(src,32);
+}
+
+
+vuint64m8_t test___riscv_vmv_v_x_u64m8(uint64_t src,size_t vl)
+{
+    return __riscv_vmv_v_x_u64m8(src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmv\.v\.x\s+v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-1.C
new file mode 100644
index 00000000000..993293cc8d0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-1.C
@@ -0,0 +1,396 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x(vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x(vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x(vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vint8m1_t test___riscv_vncvt_x(vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vint8m2_t test___riscv_vncvt_x(vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vint8m4_t test___riscv_vncvt_x(vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x(vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x(vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x(vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x(vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x(vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x(vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x(vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x(vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vint16m1_t test___riscv_vncvt_x(vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vint16m2_t test___riscv_vncvt_x(vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vint16m4_t test___riscv_vncvt_x(vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x(vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x(vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x(vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x(vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x(vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x(vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vint32m1_t test___riscv_vncvt_x(vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vint32m2_t test___riscv_vncvt_x(vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vint32m4_t test___riscv_vncvt_x(vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x(vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x(vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x(vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x(vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,vl);
+}
+
+
+vint8mf8_t test___riscv_vncvt_x(vbool64_t mask,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x(vbool32_t mask,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x(vbool16_t mask,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vint8m1_t test___riscv_vncvt_x(vbool8_t mask,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vint8m2_t test___riscv_vncvt_x(vbool4_t mask,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vint8m4_t test___riscv_vncvt_x(vbool2_t mask,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x(vbool64_t mask,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x(vbool32_t mask,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x(vbool16_t mask,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x(vbool8_t mask,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x(vbool4_t mask,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x(vbool2_t mask,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x(vbool64_t mask,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x(vbool32_t mask,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vint16m1_t test___riscv_vncvt_x(vbool16_t mask,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vint16m2_t test___riscv_vncvt_x(vbool8_t mask,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vint16m4_t test___riscv_vncvt_x(vbool4_t mask,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x(vbool64_t mask,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x(vbool32_t mask,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x(vbool16_t mask,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x(vbool8_t mask,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x(vbool4_t mask,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x(vbool64_t mask,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vint32m1_t test___riscv_vncvt_x(vbool32_t mask,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vint32m2_t test___riscv_vncvt_x(vbool16_t mask,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vint32m4_t test___riscv_vncvt_x(vbool8_t mask,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x(vbool64_t mask,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x(vbool32_t mask,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x(vbool16_t mask,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x(vbool8_t mask,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-2.C
new file mode 100644
index 00000000000..0e5030715b9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-2.C
@@ -0,0 +1,396 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x(vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x(vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x(vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vint8m1_t test___riscv_vncvt_x(vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vint8m2_t test___riscv_vncvt_x(vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vint8m4_t test___riscv_vncvt_x(vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x(vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x(vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x(vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x(vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x(vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x(vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x(vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x(vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vint16m1_t test___riscv_vncvt_x(vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vint16m2_t test___riscv_vncvt_x(vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vint16m4_t test___riscv_vncvt_x(vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x(vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x(vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x(vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x(vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x(vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x(vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vint32m1_t test___riscv_vncvt_x(vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vint32m2_t test___riscv_vncvt_x(vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vint32m4_t test___riscv_vncvt_x(vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x(vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x(vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x(vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x(vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,31);
+}
+
+
+vint8mf8_t test___riscv_vncvt_x(vbool64_t mask,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x(vbool32_t mask,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x(vbool16_t mask,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vint8m1_t test___riscv_vncvt_x(vbool8_t mask,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vint8m2_t test___riscv_vncvt_x(vbool4_t mask,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vint8m4_t test___riscv_vncvt_x(vbool2_t mask,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x(vbool64_t mask,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x(vbool32_t mask,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x(vbool16_t mask,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x(vbool8_t mask,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x(vbool4_t mask,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x(vbool2_t mask,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x(vbool64_t mask,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x(vbool32_t mask,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vint16m1_t test___riscv_vncvt_x(vbool16_t mask,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vint16m2_t test___riscv_vncvt_x(vbool8_t mask,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vint16m4_t test___riscv_vncvt_x(vbool4_t mask,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x(vbool64_t mask,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x(vbool32_t mask,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x(vbool16_t mask,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x(vbool8_t mask,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x(vbool4_t mask,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x(vbool64_t mask,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vint32m1_t test___riscv_vncvt_x(vbool32_t mask,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vint32m2_t test___riscv_vncvt_x(vbool16_t mask,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vint32m4_t test___riscv_vncvt_x(vbool8_t mask,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x(vbool64_t mask,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x(vbool32_t mask,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x(vbool16_t mask,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x(vbool8_t mask,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-3.C
new file mode 100644
index 00000000000..3706dbff82f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-3.C
@@ -0,0 +1,396 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x(vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x(vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x(vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vint8m1_t test___riscv_vncvt_x(vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vint8m2_t test___riscv_vncvt_x(vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vint8m4_t test___riscv_vncvt_x(vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x(vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x(vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x(vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x(vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x(vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x(vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x(vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x(vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vint16m1_t test___riscv_vncvt_x(vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vint16m2_t test___riscv_vncvt_x(vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vint16m4_t test___riscv_vncvt_x(vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x(vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x(vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x(vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x(vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x(vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x(vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vint32m1_t test___riscv_vncvt_x(vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vint32m2_t test___riscv_vncvt_x(vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vint32m4_t test___riscv_vncvt_x(vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x(vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x(vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x(vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x(vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(src,32);
+}
+
+
+vint8mf8_t test___riscv_vncvt_x(vbool64_t mask,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x(vbool32_t mask,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x(vbool16_t mask,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vint8m1_t test___riscv_vncvt_x(vbool8_t mask,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vint8m2_t test___riscv_vncvt_x(vbool4_t mask,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vint8m4_t test___riscv_vncvt_x(vbool2_t mask,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x(vbool64_t mask,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x(vbool32_t mask,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x(vbool16_t mask,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x(vbool8_t mask,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x(vbool4_t mask,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x(vbool2_t mask,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x(vbool64_t mask,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x(vbool32_t mask,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vint16m1_t test___riscv_vncvt_x(vbool16_t mask,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vint16m2_t test___riscv_vncvt_x(vbool8_t mask,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vint16m4_t test___riscv_vncvt_x(vbool4_t mask,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x(vbool64_t mask,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x(vbool32_t mask,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x(vbool16_t mask,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x(vbool8_t mask,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x(vbool4_t mask,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x(vbool64_t mask,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vint32m1_t test___riscv_vncvt_x(vbool32_t mask,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vint32m2_t test___riscv_vncvt_x(vbool16_t mask,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vint32m4_t test___riscv_vncvt_x(vbool8_t mask,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x(vbool64_t mask,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x(vbool32_t mask,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x(vbool16_t mask,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x(vbool8_t mask,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x(mask,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-1.C
new file mode 100644
index 00000000000..1b2b942a45c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-1.C
@@ -0,0 +1,201 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-2.C
new file mode 100644
index 00000000000..b6845860ea9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-2.C
@@ -0,0 +1,201 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-3.C
new file mode 100644
index 00000000000..64c6c84278b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-3.C
@@ -0,0 +1,201 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_mu(mask,merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-1.C
new file mode 100644
index 00000000000..cb075fa3ed4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-1.C
@@ -0,0 +1,201 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_tu(vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_tu(vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_tu(vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_tu(vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_tu(vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_tu(vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_tu(vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_tu(vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_tu(vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_tu(vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_tu(vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_tu(vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_tu(vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_tu(vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_tu(vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_tu(vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_tu(vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_tu(vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_tu(vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_tu(vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_tu(vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_tu(vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_tu(vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_tu(vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_tu(vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_tu(vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_tu(vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_tu(vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_tu(vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_tu(vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-2.C
new file mode 100644
index 00000000000..d55bdd20eb2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-2.C
@@ -0,0 +1,201 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_tu(vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_tu(vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_tu(vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_tu(vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_tu(vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_tu(vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_tu(vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_tu(vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_tu(vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_tu(vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_tu(vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_tu(vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_tu(vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_tu(vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_tu(vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_tu(vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_tu(vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_tu(vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_tu(vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_tu(vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_tu(vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_tu(vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_tu(vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_tu(vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_tu(vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_tu(vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_tu(vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_tu(vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_tu(vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_tu(vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-3.C
new file mode 100644
index 00000000000..522052cdcdb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-3.C
@@ -0,0 +1,201 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_tu(vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_tu(vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_tu(vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_tu(vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_tu(vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_tu(vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_tu(vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_tu(vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_tu(vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_tu(vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_tu(vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_tu(vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_tu(vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_tu(vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_tu(vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_tu(vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_tu(vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_tu(vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_tu(vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_tu(vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_tu(vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_tu(vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_tu(vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_tu(vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_tu(vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_tu(vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_tu(vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_tu(vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_tu(vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_tu(vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tu(merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-1.C
new file mode 100644
index 00000000000..8140224966f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-1.C
@@ -0,0 +1,201 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-2.C
new file mode 100644
index 00000000000..83cbbeeef1d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-2.C
@@ -0,0 +1,201 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-3.C
new file mode 100644
index 00000000000..80e4eb9a3d9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-3.C
@@ -0,0 +1,201 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tum(mask,merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-1.C
new file mode 100644
index 00000000000..0bfe0798e29
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-1.C
@@ -0,0 +1,201 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-2.C
new file mode 100644
index 00000000000..1166b31816a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-2.C
@@ -0,0 +1,201 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-3.C
new file mode 100644
index 00000000000..7bc41dfc51a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-3.C
@@ -0,0 +1,201 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_tumu(mask,merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */