RISC-V: Add vluxei32 C API intrinsic testcases

From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vluxei32_v-1.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v-2.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v-3.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v_tu-1.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v_tu-2.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v_tu-3.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v_tum-1.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v_tum-2.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v_tum-3.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v_tumu-1.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v_tumu-2.c: New test.
        * gcc.target/riscv/rvv/base/vluxei32_v_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vluxei32_v-1.c  | 307 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vluxei32_v-2.c  | 307 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vluxei32_v-3.c  | 307 ++++++++++++++++++
 .../riscv/rvv/base/vluxei32_v_m-1.c           | 307 ++++++++++++++++++
 .../riscv/rvv/base/vluxei32_v_m-2.c           | 307 ++++++++++++++++++
 .../riscv/rvv/base/vluxei32_v_m-3.c           | 307 ++++++++++++++++++
 .../riscv/rvv/base/vluxei32_v_mu-1.c          | 307 ++++++++++++++++++
 .../riscv/rvv/base/vluxei32_v_mu-2.c          | 307 ++++++++++++++++++
 .../riscv/rvv/base/vluxei32_v_mu-3.c          | 307 ++++++++++++++++++
 .../riscv/rvv/base/vluxei32_v_tu-1.c          | 307 ++++++++++++++++++
 .../riscv/rvv/base/vluxei32_v_tu-2.c          | 307 ++++++++++++++++++
 .../riscv/rvv/base/vluxei32_v_tu-3.c          | 307 ++++++++++++++++++
 .../riscv/rvv/base/vluxei32_v_tum-1.c         | 307 ++++++++++++++++++
 .../riscv/rvv/base/vluxei32_v_tum-2.c         | 307 ++++++++++++++++++
 .../riscv/rvv/base/vluxei32_v_tum-3.c         | 307 ++++++++++++++++++
 .../riscv/rvv/base/vluxei32_v_tumu-1.c        | 307 ++++++++++++++++++
 .../riscv/rvv/base/vluxei32_v_tumu-2.c        | 307 ++++++++++++++++++
 .../riscv/rvv/base/vluxei32_v_tumu-3.c        | 307 ++++++++++++++++++
 18 files changed, 5526 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-3.c

committed, thanks!

On Mon, Jan 30, 2023 at 7:07 AM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/base/vluxei32_v-1.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v-2.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v-3.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v_m-1.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v_m-2.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v_m-3.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v_mu-1.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v_mu-2.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v_mu-3.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v_tu-1.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v_tu-2.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v_tu-3.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v_tum-1.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v_tum-2.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v_tum-3.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v_tumu-1.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v_tumu-2.c: New test.
>         * gcc.target/riscv/rvv/base/vluxei32_v_tumu-3.c: New test.
>
> ---
>  .../gcc.target/riscv/rvv/base/vluxei32_v-1.c  | 307 ++++++++++++++++++
>  .../gcc.target/riscv/rvv/base/vluxei32_v-2.c  | 307 ++++++++++++++++++
>  .../gcc.target/riscv/rvv/base/vluxei32_v-3.c  | 307 ++++++++++++++++++
>  .../riscv/rvv/base/vluxei32_v_m-1.c           | 307 ++++++++++++++++++
>  .../riscv/rvv/base/vluxei32_v_m-2.c           | 307 ++++++++++++++++++
>  .../riscv/rvv/base/vluxei32_v_m-3.c           | 307 ++++++++++++++++++
>  .../riscv/rvv/base/vluxei32_v_mu-1.c          | 307 ++++++++++++++++++
>  .../riscv/rvv/base/vluxei32_v_mu-2.c          | 307 ++++++++++++++++++
>  .../riscv/rvv/base/vluxei32_v_mu-3.c          | 307 ++++++++++++++++++
>  .../riscv/rvv/base/vluxei32_v_tu-1.c          | 307 ++++++++++++++++++
>  .../riscv/rvv/base/vluxei32_v_tu-2.c          | 307 ++++++++++++++++++
>  .../riscv/rvv/base/vluxei32_v_tu-3.c          | 307 ++++++++++++++++++
>  .../riscv/rvv/base/vluxei32_v_tum-1.c         | 307 ++++++++++++++++++
>  .../riscv/rvv/base/vluxei32_v_tum-2.c         | 307 ++++++++++++++++++
>  .../riscv/rvv/base/vluxei32_v_tum-3.c         | 307 ++++++++++++++++++
>  .../riscv/rvv/base/vluxei32_v_tumu-1.c        | 307 ++++++++++++++++++
>  .../riscv/rvv/base/vluxei32_v_tumu-2.c        | 307 ++++++++++++++++++
>  .../riscv/rvv/base/vluxei32_v_tumu-3.c        | 307 ++++++++++++++++++
>  18 files changed, 5526 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-3.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-1.c
> new file mode 100644
> index 00000000000..2542686cd66
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-1.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8(const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8(base,bindex,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4(const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4(base,bindex,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2(const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2(base,bindex,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1(const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1(base,bindex,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2(const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2(base,bindex,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4(const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4(base,bindex,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2(const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2(base,bindex,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1(const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1(base,bindex,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2(const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2(base,bindex,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4(const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4(base,bindex,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2(const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2(base,bindex,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1(const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1(base,bindex,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2(const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2(base,bindex,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4(const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4(base,bindex,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8(const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8(base,bindex,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1(const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1(base,bindex,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2(const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2(base,bindex,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4(const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4(base,bindex,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8(const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8(base,bindex,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8(const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8(base,bindex,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4(const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4(base,bindex,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2(const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2(base,bindex,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1(const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1(base,bindex,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2(const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2(base,bindex,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4(const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4(base,bindex,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2(const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2(base,bindex,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1(const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1(base,bindex,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2(const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2(base,bindex,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4(const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4(base,bindex,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2(const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2(base,bindex,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1(const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1(base,bindex,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2(const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2(base,bindex,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4(const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4(base,bindex,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8(const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8(base,bindex,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1(const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1(base,bindex,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2(const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2(base,bindex,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4(const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4(base,bindex,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8(const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8(base,bindex,vl);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2(const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2(base,bindex,vl);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1(const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1(base,bindex,vl);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2(const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2(base,bindex,vl);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4(const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4(base,bindex,vl);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8(const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8(base,bindex,vl);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1(const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1(base,bindex,vl);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2(const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2(base,bindex,vl);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4(const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4(base,bindex,vl);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8(const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8(base,bindex,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-2.c
> new file mode 100644
> index 00000000000..f49a8d85525
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-2.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8(const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8(base,bindex,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4(const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4(base,bindex,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2(const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2(base,bindex,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1(const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1(base,bindex,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2(const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2(base,bindex,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4(const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4(base,bindex,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2(const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2(base,bindex,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1(const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1(base,bindex,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2(const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2(base,bindex,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4(const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4(base,bindex,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2(const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2(base,bindex,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1(const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1(base,bindex,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2(const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2(base,bindex,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4(const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4(base,bindex,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8(const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8(base,bindex,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1(const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1(base,bindex,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2(const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2(base,bindex,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4(const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4(base,bindex,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8(const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8(base,bindex,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8(const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8(base,bindex,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4(const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4(base,bindex,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2(const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2(base,bindex,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1(const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1(base,bindex,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2(const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2(base,bindex,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4(const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4(base,bindex,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2(const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2(base,bindex,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1(const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1(base,bindex,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2(const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2(base,bindex,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4(const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4(base,bindex,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2(const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2(base,bindex,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1(const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1(base,bindex,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2(const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2(base,bindex,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4(const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4(base,bindex,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8(const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8(base,bindex,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1(const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1(base,bindex,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2(const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2(base,bindex,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4(const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4(base,bindex,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8(const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8(base,bindex,31);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2(const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2(base,bindex,31);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1(const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1(base,bindex,31);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2(const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2(base,bindex,31);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4(const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4(base,bindex,31);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8(const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8(base,bindex,31);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1(const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1(base,bindex,31);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2(const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2(base,bindex,31);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4(const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4(base,bindex,31);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8(const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8(base,bindex,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-3.c
> new file mode 100644
> index 00000000000..945b70cf715
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-3.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8(const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8(base,bindex,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4(const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4(base,bindex,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2(const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2(base,bindex,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1(const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1(base,bindex,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2(const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2(base,bindex,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4(const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4(base,bindex,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2(const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2(base,bindex,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1(const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1(base,bindex,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2(const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2(base,bindex,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4(const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4(base,bindex,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2(const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2(base,bindex,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1(const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1(base,bindex,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2(const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2(base,bindex,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4(const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4(base,bindex,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8(const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8(base,bindex,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1(const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1(base,bindex,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2(const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2(base,bindex,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4(const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4(base,bindex,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8(const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8(base,bindex,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8(const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8(base,bindex,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4(const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4(base,bindex,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2(const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2(base,bindex,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1(const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1(base,bindex,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2(const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2(base,bindex,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4(const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4(base,bindex,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2(const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2(base,bindex,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1(const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1(base,bindex,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2(const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2(base,bindex,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4(const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4(base,bindex,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2(const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2(base,bindex,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1(const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1(base,bindex,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2(const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2(base,bindex,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4(const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4(base,bindex,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8(const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8(base,bindex,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1(const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1(base,bindex,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2(const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2(base,bindex,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4(const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4(base,bindex,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8(const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8(base,bindex,32);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2(const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2(base,bindex,32);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1(const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1(base,bindex,32);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2(const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2(base,bindex,32);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4(const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4(base,bindex,32);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8(const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8(base,bindex,32);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1(const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1(base,bindex,32);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2(const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2(base,bindex,32);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4(const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4(base,bindex,32);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8(const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8(base,bindex,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-1.c
> new file mode 100644
> index 00000000000..86a4fbdd57b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-1.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8_m(vbool64_t mask,const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4_m(vbool32_t mask,const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2_m(vbool16_t mask,const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1_m(vbool8_t mask,const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2_m(vbool4_t mask,const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4_m(vbool64_t mask,const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2_m(vbool32_t mask,const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1_m(vbool16_t mask,const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2_m(vbool8_t mask,const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4_m(vbool4_t mask,const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2_m(vbool64_t mask,const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1_m(vbool32_t mask,const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2_m(vbool16_t mask,const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4_m(vbool8_t mask,const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8_m(vbool4_t mask,const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1_m(vbool64_t mask,const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2_m(vbool32_t mask,const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4_m(vbool16_t mask,const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4_m(mask,base,bindex,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8_m(vbool8_t mask,const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8_m(vbool64_t mask,const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4_m(vbool32_t mask,const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2_m(vbool16_t mask,const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1_m(vbool8_t mask,const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2_m(vbool4_t mask,const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4_m(vbool64_t mask,const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2_m(vbool32_t mask,const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1_m(vbool16_t mask,const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2_m(vbool8_t mask,const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4_m(vbool4_t mask,const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2_m(vbool64_t mask,const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1_m(vbool32_t mask,const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2_m(vbool16_t mask,const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4_m(vbool8_t mask,const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8_m(vbool4_t mask,const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1_m(vbool64_t mask,const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2_m(vbool32_t mask,const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4_m(vbool16_t mask,const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4_m(mask,base,bindex,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8_m(vbool8_t mask,const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8_m(mask,base,bindex,vl);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2_m(vbool64_t mask,const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1_m(vbool32_t mask,const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1_m(mask,base,bindex,vl);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2_m(vbool16_t mask,const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4_m(vbool8_t mask,const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4_m(mask,base,bindex,vl);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8_m(vbool4_t mask,const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8_m(mask,base,bindex,vl);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1_m(vbool64_t mask,const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1_m(mask,base,bindex,vl);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2_m(vbool32_t mask,const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2_m(mask,base,bindex,vl);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4_m(vbool16_t mask,const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4_m(mask,base,bindex,vl);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8_m(vbool8_t mask,const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8_m(mask,base,bindex,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-2.c
> new file mode 100644
> index 00000000000..02df1ba6e4a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-2.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8_m(vbool64_t mask,const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8_m(mask,base,bindex,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4_m(vbool32_t mask,const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4_m(mask,base,bindex,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2_m(vbool16_t mask,const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2_m(mask,base,bindex,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1_m(vbool8_t mask,const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1_m(mask,base,bindex,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2_m(vbool4_t mask,const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2_m(mask,base,bindex,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4_m(vbool64_t mask,const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4_m(mask,base,bindex,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2_m(vbool32_t mask,const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2_m(mask,base,bindex,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1_m(vbool16_t mask,const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1_m(mask,base,bindex,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2_m(vbool8_t mask,const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2_m(mask,base,bindex,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4_m(vbool4_t mask,const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4_m(mask,base,bindex,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2_m(vbool64_t mask,const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2_m(mask,base,bindex,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1_m(vbool32_t mask,const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1_m(mask,base,bindex,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2_m(vbool16_t mask,const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2_m(mask,base,bindex,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4_m(vbool8_t mask,const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4_m(mask,base,bindex,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8_m(vbool4_t mask,const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8_m(mask,base,bindex,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1_m(vbool64_t mask,const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1_m(mask,base,bindex,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2_m(vbool32_t mask,const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2_m(mask,base,bindex,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4_m(vbool16_t mask,const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4_m(mask,base,bindex,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8_m(vbool8_t mask,const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8_m(vbool64_t mask,const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4_m(vbool32_t mask,const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2_m(vbool16_t mask,const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1_m(vbool8_t mask,const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2_m(vbool4_t mask,const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4_m(vbool64_t mask,const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2_m(vbool32_t mask,const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1_m(vbool16_t mask,const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2_m(vbool8_t mask,const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4_m(vbool4_t mask,const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2_m(vbool64_t mask,const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1_m(vbool32_t mask,const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2_m(vbool16_t mask,const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4_m(vbool8_t mask,const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8_m(vbool4_t mask,const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1_m(vbool64_t mask,const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2_m(vbool32_t mask,const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4_m(vbool16_t mask,const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4_m(mask,base,bindex,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8_m(vbool8_t mask,const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8_m(mask,base,bindex,31);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2_m(vbool64_t mask,const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2_m(mask,base,bindex,31);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1_m(vbool32_t mask,const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1_m(mask,base,bindex,31);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2_m(vbool16_t mask,const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2_m(mask,base,bindex,31);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4_m(vbool8_t mask,const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4_m(mask,base,bindex,31);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8_m(vbool4_t mask,const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8_m(mask,base,bindex,31);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1_m(vbool64_t mask,const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1_m(mask,base,bindex,31);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2_m(vbool32_t mask,const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2_m(mask,base,bindex,31);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4_m(vbool16_t mask,const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4_m(mask,base,bindex,31);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8_m(vbool8_t mask,const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8_m(mask,base,bindex,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-3.c
> new file mode 100644
> index 00000000000..976ac99714f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-3.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8_m(vbool64_t mask,const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8_m(mask,base,bindex,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4_m(vbool32_t mask,const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4_m(mask,base,bindex,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2_m(vbool16_t mask,const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2_m(mask,base,bindex,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1_m(vbool8_t mask,const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1_m(mask,base,bindex,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2_m(vbool4_t mask,const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2_m(mask,base,bindex,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4_m(vbool64_t mask,const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4_m(mask,base,bindex,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2_m(vbool32_t mask,const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2_m(mask,base,bindex,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1_m(vbool16_t mask,const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1_m(mask,base,bindex,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2_m(vbool8_t mask,const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2_m(mask,base,bindex,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4_m(vbool4_t mask,const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4_m(mask,base,bindex,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2_m(vbool64_t mask,const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2_m(mask,base,bindex,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1_m(vbool32_t mask,const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1_m(mask,base,bindex,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2_m(vbool16_t mask,const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2_m(mask,base,bindex,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4_m(vbool8_t mask,const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4_m(mask,base,bindex,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8_m(vbool4_t mask,const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8_m(mask,base,bindex,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1_m(vbool64_t mask,const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1_m(mask,base,bindex,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2_m(vbool32_t mask,const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2_m(mask,base,bindex,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4_m(vbool16_t mask,const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4_m(mask,base,bindex,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8_m(vbool8_t mask,const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8_m(vbool64_t mask,const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4_m(vbool32_t mask,const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2_m(vbool16_t mask,const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1_m(vbool8_t mask,const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2_m(vbool4_t mask,const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4_m(vbool64_t mask,const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2_m(vbool32_t mask,const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1_m(vbool16_t mask,const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2_m(vbool8_t mask,const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4_m(vbool4_t mask,const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2_m(vbool64_t mask,const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1_m(vbool32_t mask,const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2_m(vbool16_t mask,const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4_m(vbool8_t mask,const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8_m(vbool4_t mask,const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1_m(vbool64_t mask,const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2_m(vbool32_t mask,const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4_m(vbool16_t mask,const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4_m(mask,base,bindex,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8_m(vbool8_t mask,const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8_m(mask,base,bindex,32);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2_m(vbool64_t mask,const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2_m(mask,base,bindex,32);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1_m(vbool32_t mask,const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1_m(mask,base,bindex,32);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2_m(vbool16_t mask,const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2_m(mask,base,bindex,32);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4_m(vbool8_t mask,const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4_m(mask,base,bindex,32);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8_m(vbool4_t mask,const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8_m(mask,base,bindex,32);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1_m(vbool64_t mask,const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1_m(mask,base,bindex,32);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2_m(vbool32_t mask,const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2_m(mask,base,bindex,32);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4_m(vbool16_t mask,const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4_m(mask,base,bindex,32);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8_m(vbool8_t mask,const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8_m(mask,base,bindex,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-1.c
> new file mode 100644
> index 00000000000..86490559c16
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-1.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1_mu(vbool8_t mask,vint8m1_t merge,const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2_mu(vbool4_t mask,vint8m2_t merge,const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1_mu(vbool16_t mask,vint16m1_t merge,const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2_mu(vbool8_t mask,vint16m2_t merge,const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4_mu(vbool4_t mask,vint16m4_t merge,const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1_mu(vbool32_t mask,vint32m1_t merge,const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2_mu(vbool16_t mask,vint32m2_t merge,const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4_mu(vbool8_t mask,vint32m4_t merge,const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8_mu(vbool4_t mask,vint32m8_t merge,const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1_mu(vbool64_t mask,vint64m1_t merge,const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2_mu(vbool32_t mask,vint64m2_t merge,const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4_mu(vbool16_t mask,vint64m4_t merge,const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8_mu(vbool8_t mask,vint64m8_t merge,const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1_mu(vbool8_t mask,vuint8m1_t merge,const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2_mu(vbool4_t mask,vuint8m2_t merge,const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1_mu(vbool16_t mask,vuint16m1_t merge,const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2_mu(vbool8_t mask,vuint16m2_t merge,const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4_mu(vbool4_t mask,vuint16m4_t merge,const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1_mu(vbool32_t mask,vuint32m1_t merge,const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2_mu(vbool16_t mask,vuint32m2_t merge,const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4_mu(vbool8_t mask,vuint32m4_t merge,const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8_mu(vbool4_t mask,vuint32m8_t merge,const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1_mu(vbool64_t mask,vuint64m1_t merge,const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2_mu(vbool32_t mask,vuint64m2_t merge,const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4_mu(vbool16_t mask,vuint64m4_t merge,const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8_mu(vbool8_t mask,vuint64m8_t merge,const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2_mu(vbool64_t mask,vfloat32mf2_t merge,const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1_mu(vbool32_t mask,vfloat32m1_t merge,const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2_mu(vbool16_t mask,vfloat32m2_t merge,const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4_mu(vbool8_t mask,vfloat32m4_t merge,const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8_mu(vbool4_t mask,vfloat32m8_t merge,const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1_mu(vbool64_t mask,vfloat64m1_t merge,const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2_mu(vbool32_t mask,vfloat64m2_t merge,const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4_mu(vbool16_t mask,vfloat64m4_t merge,const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8_mu(vbool8_t mask,vfloat64m8_t merge,const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8_mu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-2.c
> new file mode 100644
> index 00000000000..9f9544cbcb9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-2.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1_mu(vbool8_t mask,vint8m1_t merge,const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2_mu(vbool4_t mask,vint8m2_t merge,const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1_mu(vbool16_t mask,vint16m1_t merge,const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2_mu(vbool8_t mask,vint16m2_t merge,const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4_mu(vbool4_t mask,vint16m4_t merge,const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1_mu(vbool32_t mask,vint32m1_t merge,const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2_mu(vbool16_t mask,vint32m2_t merge,const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4_mu(vbool8_t mask,vint32m4_t merge,const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8_mu(vbool4_t mask,vint32m8_t merge,const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1_mu(vbool64_t mask,vint64m1_t merge,const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2_mu(vbool32_t mask,vint64m2_t merge,const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4_mu(vbool16_t mask,vint64m4_t merge,const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8_mu(vbool8_t mask,vint64m8_t merge,const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1_mu(vbool8_t mask,vuint8m1_t merge,const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2_mu(vbool4_t mask,vuint8m2_t merge,const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1_mu(vbool16_t mask,vuint16m1_t merge,const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2_mu(vbool8_t mask,vuint16m2_t merge,const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4_mu(vbool4_t mask,vuint16m4_t merge,const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1_mu(vbool32_t mask,vuint32m1_t merge,const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2_mu(vbool16_t mask,vuint32m2_t merge,const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4_mu(vbool8_t mask,vuint32m4_t merge,const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8_mu(vbool4_t mask,vuint32m8_t merge,const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1_mu(vbool64_t mask,vuint64m1_t merge,const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2_mu(vbool32_t mask,vuint64m2_t merge,const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4_mu(vbool16_t mask,vuint64m4_t merge,const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8_mu(vbool8_t mask,vuint64m8_t merge,const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2_mu(vbool64_t mask,vfloat32mf2_t merge,const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1_mu(vbool32_t mask,vfloat32m1_t merge,const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2_mu(vbool16_t mask,vfloat32m2_t merge,const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4_mu(vbool8_t mask,vfloat32m4_t merge,const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8_mu(vbool4_t mask,vfloat32m8_t merge,const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1_mu(vbool64_t mask,vfloat64m1_t merge,const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2_mu(vbool32_t mask,vfloat64m2_t merge,const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4_mu(vbool16_t mask,vfloat64m4_t merge,const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8_mu(vbool8_t mask,vfloat64m8_t merge,const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8_mu(mask,merge,base,bindex,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-3.c
> new file mode 100644
> index 00000000000..193afcfa23b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-3.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1_mu(vbool8_t mask,vint8m1_t merge,const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2_mu(vbool4_t mask,vint8m2_t merge,const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1_mu(vbool16_t mask,vint16m1_t merge,const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2_mu(vbool8_t mask,vint16m2_t merge,const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4_mu(vbool4_t mask,vint16m4_t merge,const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1_mu(vbool32_t mask,vint32m1_t merge,const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2_mu(vbool16_t mask,vint32m2_t merge,const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4_mu(vbool8_t mask,vint32m4_t merge,const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8_mu(vbool4_t mask,vint32m8_t merge,const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1_mu(vbool64_t mask,vint64m1_t merge,const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2_mu(vbool32_t mask,vint64m2_t merge,const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4_mu(vbool16_t mask,vint64m4_t merge,const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8_mu(vbool8_t mask,vint64m8_t merge,const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1_mu(vbool8_t mask,vuint8m1_t merge,const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2_mu(vbool4_t mask,vuint8m2_t merge,const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1_mu(vbool16_t mask,vuint16m1_t merge,const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2_mu(vbool8_t mask,vuint16m2_t merge,const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4_mu(vbool4_t mask,vuint16m4_t merge,const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1_mu(vbool32_t mask,vuint32m1_t merge,const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2_mu(vbool16_t mask,vuint32m2_t merge,const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4_mu(vbool8_t mask,vuint32m4_t merge,const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8_mu(vbool4_t mask,vuint32m8_t merge,const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1_mu(vbool64_t mask,vuint64m1_t merge,const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2_mu(vbool32_t mask,vuint64m2_t merge,const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4_mu(vbool16_t mask,vuint64m4_t merge,const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8_mu(vbool8_t mask,vuint64m8_t merge,const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2_mu(vbool64_t mask,vfloat32mf2_t merge,const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1_mu(vbool32_t mask,vfloat32m1_t merge,const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2_mu(vbool16_t mask,vfloat32m2_t merge,const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4_mu(vbool8_t mask,vfloat32m4_t merge,const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8_mu(vbool4_t mask,vfloat32m8_t merge,const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1_mu(vbool64_t mask,vfloat64m1_t merge,const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2_mu(vbool32_t mask,vfloat64m2_t merge,const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4_mu(vbool16_t mask,vfloat64m4_t merge,const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8_mu(vbool8_t mask,vfloat64m8_t merge,const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8_mu(mask,merge,base,bindex,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-1.c
> new file mode 100644
> index 00000000000..f754e65f4b0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-1.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8_tu(vint8mf8_t merge,const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4_tu(vint8mf4_t merge,const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2_tu(vint8mf2_t merge,const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1_tu(vint8m1_t merge,const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2_tu(vint8m2_t merge,const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4_tu(vint16mf4_t merge,const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2_tu(vint16mf2_t merge,const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1_tu(vint16m1_t merge,const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2_tu(vint16m2_t merge,const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4_tu(vint16m4_t merge,const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2_tu(vint32mf2_t merge,const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1_tu(vint32m1_t merge,const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2_tu(vint32m2_t merge,const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4_tu(vint32m4_t merge,const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8_tu(vint32m8_t merge,const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1_tu(vint64m1_t merge,const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2_tu(vint64m2_t merge,const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4_tu(vint64m4_t merge,const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8_tu(vint64m8_t merge,const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8_tu(vuint8mf8_t merge,const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4_tu(vuint8mf4_t merge,const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2_tu(vuint8mf2_t merge,const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1_tu(vuint8m1_t merge,const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2_tu(vuint8m2_t merge,const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4_tu(vuint16mf4_t merge,const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2_tu(vuint16mf2_t merge,const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1_tu(vuint16m1_t merge,const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2_tu(vuint16m2_t merge,const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4_tu(vuint16m4_t merge,const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2_tu(vuint32mf2_t merge,const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1_tu(vuint32m1_t merge,const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2_tu(vuint32m2_t merge,const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4_tu(vuint32m4_t merge,const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8_tu(vuint32m8_t merge,const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1_tu(vuint64m1_t merge,const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2_tu(vuint64m2_t merge,const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4_tu(vuint64m4_t merge,const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8_tu(vuint64m8_t merge,const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2_tu(vfloat32mf2_t merge,const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1_tu(vfloat32m1_t merge,const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2_tu(vfloat32m2_t merge,const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4_tu(vfloat32m4_t merge,const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8_tu(vfloat32m8_t merge,const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1_tu(vfloat64m1_t merge,const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2_tu(vfloat64m2_t merge,const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4_tu(vfloat64m4_t merge,const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4_tu(merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8_tu(vfloat64m8_t merge,const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8_tu(merge,base,bindex,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-2.c
> new file mode 100644
> index 00000000000..e87d249096f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-2.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8_tu(vint8mf8_t merge,const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4_tu(vint8mf4_t merge,const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2_tu(vint8mf2_t merge,const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1_tu(vint8m1_t merge,const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2_tu(vint8m2_t merge,const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4_tu(vint16mf4_t merge,const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2_tu(vint16mf2_t merge,const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1_tu(vint16m1_t merge,const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2_tu(vint16m2_t merge,const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4_tu(vint16m4_t merge,const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2_tu(vint32mf2_t merge,const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1_tu(vint32m1_t merge,const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2_tu(vint32m2_t merge,const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4_tu(vint32m4_t merge,const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8_tu(vint32m8_t merge,const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1_tu(vint64m1_t merge,const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2_tu(vint64m2_t merge,const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4_tu(vint64m4_t merge,const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4_tu(merge,base,bindex,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8_tu(vint64m8_t merge,const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8_tu(vuint8mf8_t merge,const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4_tu(vuint8mf4_t merge,const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2_tu(vuint8mf2_t merge,const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1_tu(vuint8m1_t merge,const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2_tu(vuint8m2_t merge,const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4_tu(vuint16mf4_t merge,const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2_tu(vuint16mf2_t merge,const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1_tu(vuint16m1_t merge,const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2_tu(vuint16m2_t merge,const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4_tu(vuint16m4_t merge,const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2_tu(vuint32mf2_t merge,const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1_tu(vuint32m1_t merge,const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2_tu(vuint32m2_t merge,const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4_tu(vuint32m4_t merge,const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8_tu(vuint32m8_t merge,const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1_tu(vuint64m1_t merge,const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2_tu(vuint64m2_t merge,const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4_tu(vuint64m4_t merge,const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4_tu(merge,base,bindex,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8_tu(vuint64m8_t merge,const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8_tu(merge,base,bindex,31);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2_tu(vfloat32mf2_t merge,const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1_tu(vfloat32m1_t merge,const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1_tu(merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2_tu(vfloat32m2_t merge,const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4_tu(vfloat32m4_t merge,const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4_tu(merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8_tu(vfloat32m8_t merge,const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8_tu(merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1_tu(vfloat64m1_t merge,const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1_tu(merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2_tu(vfloat64m2_t merge,const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2_tu(merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4_tu(vfloat64m4_t merge,const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4_tu(merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8_tu(vfloat64m8_t merge,const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8_tu(merge,base,bindex,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-3.c
> new file mode 100644
> index 00000000000..4f68a5f8cf8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-3.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8_tu(vint8mf8_t merge,const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4_tu(vint8mf4_t merge,const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2_tu(vint8mf2_t merge,const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1_tu(vint8m1_t merge,const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2_tu(vint8m2_t merge,const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4_tu(vint16mf4_t merge,const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2_tu(vint16mf2_t merge,const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1_tu(vint16m1_t merge,const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2_tu(vint16m2_t merge,const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4_tu(vint16m4_t merge,const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2_tu(vint32mf2_t merge,const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1_tu(vint32m1_t merge,const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2_tu(vint32m2_t merge,const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4_tu(vint32m4_t merge,const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8_tu(vint32m8_t merge,const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1_tu(vint64m1_t merge,const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2_tu(vint64m2_t merge,const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4_tu(vint64m4_t merge,const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4_tu(merge,base,bindex,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8_tu(vint64m8_t merge,const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8_tu(vuint8mf8_t merge,const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4_tu(vuint8mf4_t merge,const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2_tu(vuint8mf2_t merge,const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1_tu(vuint8m1_t merge,const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2_tu(vuint8m2_t merge,const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4_tu(vuint16mf4_t merge,const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2_tu(vuint16mf2_t merge,const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1_tu(vuint16m1_t merge,const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2_tu(vuint16m2_t merge,const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4_tu(vuint16m4_t merge,const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2_tu(vuint32mf2_t merge,const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1_tu(vuint32m1_t merge,const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2_tu(vuint32m2_t merge,const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4_tu(vuint32m4_t merge,const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8_tu(vuint32m8_t merge,const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1_tu(vuint64m1_t merge,const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2_tu(vuint64m2_t merge,const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4_tu(vuint64m4_t merge,const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4_tu(merge,base,bindex,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8_tu(vuint64m8_t merge,const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8_tu(merge,base,bindex,32);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2_tu(vfloat32mf2_t merge,const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1_tu(vfloat32m1_t merge,const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1_tu(merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2_tu(vfloat32m2_t merge,const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4_tu(vfloat32m4_t merge,const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4_tu(merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8_tu(vfloat32m8_t merge,const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8_tu(merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1_tu(vfloat64m1_t merge,const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1_tu(merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2_tu(vfloat64m2_t merge,const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2_tu(merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4_tu(vfloat64m4_t merge,const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4_tu(merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8_tu(vfloat64m8_t merge,const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8_tu(merge,base,bindex,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-1.c
> new file mode 100644
> index 00000000000..22dee056019
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-1.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1_tum(vbool8_t mask,vint8m1_t merge,const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2_tum(vbool4_t mask,vint8m2_t merge,const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1_tum(vbool8_t mask,vuint8m1_t merge,const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2_tum(vbool4_t mask,vuint8m2_t merge,const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1_tum(vbool16_t mask,vuint16m1_t merge,const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2_tum(vbool8_t mask,vuint16m2_t merge,const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4_tum(vbool4_t mask,vuint16m4_t merge,const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1_tum(vbool32_t mask,vuint32m1_t merge,const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2_tum(vbool16_t mask,vuint32m2_t merge,const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4_tum(vbool8_t mask,vuint32m4_t merge,const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8_tum(vbool4_t mask,vuint32m8_t merge,const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1_tum(vbool64_t mask,vuint64m1_t merge,const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2_tum(vbool32_t mask,vuint64m2_t merge,const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4_tum(vbool16_t mask,vuint64m4_t merge,const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8_tum(vbool8_t mask,vuint64m8_t merge,const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2_tum(vbool64_t mask,vfloat32mf2_t merge,const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1_tum(vbool32_t mask,vfloat32m1_t merge,const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2_tum(vbool16_t mask,vfloat32m2_t merge,const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4_tum(vbool8_t mask,vfloat32m4_t merge,const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8_tum(vbool4_t mask,vfloat32m8_t merge,const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1_tum(vbool64_t mask,vfloat64m1_t merge,const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2_tum(vbool32_t mask,vfloat64m2_t merge,const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4_tum(vbool16_t mask,vfloat64m4_t merge,const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8_tum(vbool8_t mask,vfloat64m8_t merge,const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8_tum(mask,merge,base,bindex,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-2.c
> new file mode 100644
> index 00000000000..d408ab7b823
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-2.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1_tum(vbool8_t mask,vint8m1_t merge,const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2_tum(vbool4_t mask,vint8m2_t merge,const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1_tum(vbool8_t mask,vuint8m1_t merge,const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2_tum(vbool4_t mask,vuint8m2_t merge,const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1_tum(vbool16_t mask,vuint16m1_t merge,const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2_tum(vbool8_t mask,vuint16m2_t merge,const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4_tum(vbool4_t mask,vuint16m4_t merge,const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1_tum(vbool32_t mask,vuint32m1_t merge,const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2_tum(vbool16_t mask,vuint32m2_t merge,const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4_tum(vbool8_t mask,vuint32m4_t merge,const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8_tum(vbool4_t mask,vuint32m8_t merge,const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1_tum(vbool64_t mask,vuint64m1_t merge,const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2_tum(vbool32_t mask,vuint64m2_t merge,const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4_tum(vbool16_t mask,vuint64m4_t merge,const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8_tum(vbool8_t mask,vuint64m8_t merge,const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2_tum(vbool64_t mask,vfloat32mf2_t merge,const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1_tum(vbool32_t mask,vfloat32m1_t merge,const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2_tum(vbool16_t mask,vfloat32m2_t merge,const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4_tum(vbool8_t mask,vfloat32m4_t merge,const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8_tum(vbool4_t mask,vfloat32m8_t merge,const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1_tum(vbool64_t mask,vfloat64m1_t merge,const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2_tum(vbool32_t mask,vfloat64m2_t merge,const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4_tum(vbool16_t mask,vfloat64m4_t merge,const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8_tum(vbool8_t mask,vfloat64m8_t merge,const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8_tum(mask,merge,base,bindex,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-3.c
> new file mode 100644
> index 00000000000..c3732b93159
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-3.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1_tum(vbool8_t mask,vint8m1_t merge,const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2_tum(vbool4_t mask,vint8m2_t merge,const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1_tum(vbool8_t mask,vuint8m1_t merge,const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2_tum(vbool4_t mask,vuint8m2_t merge,const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1_tum(vbool16_t mask,vuint16m1_t merge,const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2_tum(vbool8_t mask,vuint16m2_t merge,const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4_tum(vbool4_t mask,vuint16m4_t merge,const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1_tum(vbool32_t mask,vuint32m1_t merge,const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2_tum(vbool16_t mask,vuint32m2_t merge,const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4_tum(vbool8_t mask,vuint32m4_t merge,const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8_tum(vbool4_t mask,vuint32m8_t merge,const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1_tum(vbool64_t mask,vuint64m1_t merge,const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2_tum(vbool32_t mask,vuint64m2_t merge,const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4_tum(vbool16_t mask,vuint64m4_t merge,const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8_tum(vbool8_t mask,vuint64m8_t merge,const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2_tum(vbool64_t mask,vfloat32mf2_t merge,const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1_tum(vbool32_t mask,vfloat32m1_t merge,const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2_tum(vbool16_t mask,vfloat32m2_t merge,const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4_tum(vbool8_t mask,vfloat32m4_t merge,const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8_tum(vbool4_t mask,vfloat32m8_t merge,const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1_tum(vbool64_t mask,vfloat64m1_t merge,const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2_tum(vbool32_t mask,vfloat64m2_t merge,const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4_tum(vbool16_t mask,vfloat64m4_t merge,const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8_tum(vbool8_t mask,vfloat64m8_t merge,const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8_tum(mask,merge,base,bindex,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-1.c
> new file mode 100644
> index 00000000000..7cd8c40f6fa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-1.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1_tumu(vbool8_t mask,vint8m1_t merge,const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2_tumu(vbool4_t mask,vint8m2_t merge,const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1_tumu(vbool16_t mask,vint16m1_t merge,const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2_tumu(vbool8_t mask,vint16m2_t merge,const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4_tumu(vbool4_t mask,vint16m4_t merge,const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1_tumu(vbool32_t mask,vint32m1_t merge,const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2_tumu(vbool16_t mask,vint32m2_t merge,const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4_tumu(vbool8_t mask,vint32m4_t merge,const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8_tumu(vbool4_t mask,vint32m8_t merge,const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1_tumu(vbool64_t mask,vint64m1_t merge,const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2_tumu(vbool32_t mask,vint64m2_t merge,const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4_tumu(vbool16_t mask,vint64m4_t merge,const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8_tumu(vbool8_t mask,vint64m8_t merge,const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2_tumu(vbool64_t mask,vfloat32mf2_t merge,const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1_tumu(vbool32_t mask,vfloat32m1_t merge,const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2_tumu(vbool16_t mask,vfloat32m2_t merge,const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4_tumu(vbool8_t mask,vfloat32m4_t merge,const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8_tumu(vbool4_t mask,vfloat32m8_t merge,const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1_tumu(vbool64_t mask,vfloat64m1_t merge,const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2_tumu(vbool32_t mask,vfloat64m2_t merge,const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4_tumu(vbool16_t mask,vfloat64m4_t merge,const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8_tumu(vbool8_t mask,vfloat64m8_t merge,const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8_tumu(mask,merge,base,bindex,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-2.c
> new file mode 100644
> index 00000000000..cdd8374d3bf
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-2.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1_tumu(vbool8_t mask,vint8m1_t merge,const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2_tumu(vbool4_t mask,vint8m2_t merge,const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1_tumu(vbool16_t mask,vint16m1_t merge,const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2_tumu(vbool8_t mask,vint16m2_t merge,const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4_tumu(vbool4_t mask,vint16m4_t merge,const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1_tumu(vbool32_t mask,vint32m1_t merge,const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2_tumu(vbool16_t mask,vint32m2_t merge,const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4_tumu(vbool8_t mask,vint32m4_t merge,const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8_tumu(vbool4_t mask,vint32m8_t merge,const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1_tumu(vbool64_t mask,vint64m1_t merge,const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2_tumu(vbool32_t mask,vint64m2_t merge,const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4_tumu(vbool16_t mask,vint64m4_t merge,const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8_tumu(vbool8_t mask,vint64m8_t merge,const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2_tumu(vbool64_t mask,vfloat32mf2_t merge,const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1_tumu(vbool32_t mask,vfloat32m1_t merge,const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2_tumu(vbool16_t mask,vfloat32m2_t merge,const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4_tumu(vbool8_t mask,vfloat32m4_t merge,const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8_tumu(vbool4_t mask,vfloat32m8_t merge,const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1_tumu(vbool64_t mask,vfloat64m1_t merge,const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2_tumu(vbool32_t mask,vfloat64m2_t merge,const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4_tumu(vbool16_t mask,vfloat64m4_t merge,const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8_tumu(vbool8_t mask,vfloat64m8_t merge,const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8_tumu(mask,merge,base,bindex,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-3.c
> new file mode 100644
> index 00000000000..731ae4ca35d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-3.c
> @@ -0,0 +1,307 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vluxei32_v_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,const int8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf8_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vluxei32_v_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,const int8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf4_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vluxei32_v_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,const int8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8mf2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vluxei32_v_i8m1_tumu(vbool8_t mask,vint8m1_t merge,const int8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m1_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vluxei32_v_i8m2_tumu(vbool4_t mask,vint8m2_t merge,const int8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i8m2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vluxei32_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,const int16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf4_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vluxei32_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,const int16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16mf2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vluxei32_v_i16m1_tumu(vbool16_t mask,vint16m1_t merge,const int16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m1_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vluxei32_v_i16m2_tumu(vbool8_t mask,vint16m2_t merge,const int16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vluxei32_v_i16m4_tumu(vbool4_t mask,vint16m4_t merge,const int16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i16m4_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vluxei32_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,const int32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32mf2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vluxei32_v_i32m1_tumu(vbool32_t mask,vint32m1_t merge,const int32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m1_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vluxei32_v_i32m2_tumu(vbool16_t mask,vint32m2_t merge,const int32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vluxei32_v_i32m4_tumu(vbool8_t mask,vint32m4_t merge,const int32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m4_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vluxei32_v_i32m8_tumu(vbool4_t mask,vint32m8_t merge,const int32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i32m8_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vluxei32_v_i64m1_tumu(vbool64_t mask,vint64m1_t merge,const int64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m1_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vluxei32_v_i64m2_tumu(vbool32_t mask,vint64m2_t merge,const int64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vluxei32_v_i64m4_tumu(vbool16_t mask,vint64m4_t merge,const int64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m4_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vluxei32_v_i64m8_tumu(vbool8_t mask,vint64m8_t merge,const int64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_i64m8_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vluxei32_v_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,const uint8_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf8_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vluxei32_v_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,const uint8_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf4_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vluxei32_v_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,const uint8_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8mf2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vluxei32_v_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,const uint8_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m1_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vluxei32_v_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,const uint8_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u8m2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vluxei32_v_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,const uint16_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf4_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vluxei32_v_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,const uint16_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16mf2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vluxei32_v_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,const uint16_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m1_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vluxei32_v_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,const uint16_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vluxei32_v_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,const uint16_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u16m4_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vluxei32_v_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,const uint32_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32mf2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vluxei32_v_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,const uint32_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m1_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vluxei32_v_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,const uint32_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vluxei32_v_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,const uint32_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m4_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vluxei32_v_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,const uint32_t* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u32m8_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vluxei32_v_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,const uint64_t* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m1_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vluxei32_v_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,const uint64_t* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vluxei32_v_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,const uint64_t* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m4_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vluxei32_v_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,const uint64_t* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_u64m8_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat32mf2_t test___riscv_vluxei32_v_f32mf2_tumu(vbool64_t mask,vfloat32mf2_t merge,const float* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32mf2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m1_t test___riscv_vluxei32_v_f32m1_tumu(vbool32_t mask,vfloat32m1_t merge,const float* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m1_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m2_t test___riscv_vluxei32_v_f32m2_tumu(vbool16_t mask,vfloat32m2_t merge,const float* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m4_t test___riscv_vluxei32_v_f32m4_tumu(vbool8_t mask,vfloat32m4_t merge,const float* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m4_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat32m8_t test___riscv_vluxei32_v_f32m8_tumu(vbool4_t mask,vfloat32m8_t merge,const float* base,vuint32m8_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f32m8_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m1_t test___riscv_vluxei32_v_f64m1_tumu(vbool64_t mask,vfloat64m1_t merge,const double* base,vuint32mf2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m1_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m2_t test___riscv_vluxei32_v_f64m2_tumu(vbool32_t mask,vfloat64m2_t merge,const double* base,vuint32m1_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m2_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m4_t test___riscv_vluxei32_v_f64m4_tumu(vbool16_t mask,vfloat64m4_t merge,const double* base,vuint32m2_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m4_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +vfloat64m8_t test___riscv_vluxei32_v_f64m8_tumu(vbool8_t mask,vfloat64m8_t merge,const double* base,vuint32m4_t bindex,size_t vl)
> +{
> +    return __riscv_vluxei32_v_f64m8_tumu(mask,merge,base,bindex,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vluxei32\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} 3 } } */
> --
> 2.36.1
>