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Sun, 29 Jan 2023 15:37:40 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by sourceware.org (Postfix) with ESMTPS id 3FF073858D32 for ; Sun, 29 Jan 2023 15:37:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3FF073858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1675006643tdlifkkc Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Sun, 29 Jan 2023 23:37:22 +0800 (CST) X-QQ-SSF: 01400000002000E0L000B00A0000000 X-QQ-FEAT: RFp2QSjOiS5qZzdHxj4IIVm7ELmdcFsGDECTSSxSwLMUB3HDdpG6tAuaizhFc xdN16SShWl9t0l5Us8F8rSJxngDnki2puCeK1zJiGlhThrIVtcBZhXGrNPCQ9p0wiAjFO8z vVqR9SYBV4tqRuuZdlZBGP9Pe31ExZGOJGBbAn51pR2JDDlEdH7WeVDrpTClDteL8VZxOGt GPvad39WSffdwtq3yyF/oTv2NvR2/lwbAoy0UjvgGcHSgM/1ec0dtuOMwtRZoOXjIJpRlZO c6StrccHqZw9Mn407OtCiEnLa8LDQ97KyU1AeA7zuivuYCXx8FeQ2AA1my3nu4tY9wbI6qa IVhTO3sTY21gIbuFcVXxfabawZpEz1UGmlsGjFtmUoJGeIb4rdF2t5x8+WGfQEOfpiyYPKj n7FNlu6tBhk= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add indexed loads/stores constraints testcases Date: Sun, 29 Jan 2023 23:37:21 +0800 Message-Id: <20230129153721.220810-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c: New test. --- .../riscv/rvv/base/vlxei-vsxei-constraint-1.c | 121 ++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c new file mode 100644 index 00000000000..56e599391fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c @@ -0,0 +1,121 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\s+zero,4,e32,mf2,tu,m[au] +** vlse32\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero +** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ +** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ +** ret +*/ +void f1 (void * in, void * in2, void *out) +{ + vfloat32mf2_t v = __riscv_vlse32_v_f32mf2 (in, 0, 4); + vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4); + vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2_tu (v, in, index, 4); + __riscv_vsoxei8_v_f32mf2 (out, index, v2, 4); +} + +/* +** f2: +** vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au] +** vlm\.v\s+v[0-9]+,\s*0\([a-x0-9]+\) +** vsetivli\s+zero,4,e32,mf2,\s*t[au],\s*m[au] +** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+,v0.t +** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ +** ret +*/ +void f2 (void * in, void * in2, void *out) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vfloat32mf2_t v = __riscv_vlse32_v_f32mf2 (in, 0, 4); + vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4); + vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2_m (mask, in, index, 4); + __riscv_vsoxei8_v_f32mf2 (out, index, v2, 4); +} + +/* +** f3: +** vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au] +** vlm\.v\s+v[0-9]+,\s*0\([a-x0-9]+\) +** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*tu,\s*mu +** vlse32\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero +** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+,v0.t +** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ +** ret +*/ +void f3 (void * in, void * in2, void *out) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vfloat32mf2_t v = __riscv_vlse32_v_f32mf2 (in, 0, 4); + vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4); + vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2_tumu (mask, v, in, index, 4); + __riscv_vsoxei8_v_f32mf2 (out, index, v2, 4); +} + +/* +** f4: +** vsetivli\s+zero,4,e8,mf8,tu,\s*m[au] +** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),zero +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ +** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ +** ret +*/ +void f4 (void * in, void * in2, void *out) +{ + vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4); + vint8mf8_t v = __riscv_vluxei8_v_i8mf8 (in, index, 4); + vint8mf8_t v2 = __riscv_vluxei8_v_i8mf8_tu (v, in, index, 4); + __riscv_vsoxei8_v_i8mf8 (out, index, v2, 4); +} + +/* +** f5: +** vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au] +** vlm\.v\s+v[0-9]+,\s*0\([a-x0-9]+\) +** vsetivli\s+zero,4,e8,mf8,t[au],m[au] +** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),zero +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+,v0.t +** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ +** ret +*/ +void f5 (void * in, void * in2, void *out) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4); + vint8mf8_t v = __riscv_vluxei8_v_i8mf8 (in, index, 4); + vint8mf8_t v2 = __riscv_vluxei8_v_i8mf8_m (mask, in, index, 4); + __riscv_vsoxei8_v_i8mf8 (out, index, v2, 4); +} + +/* +** f6: +** vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au] +** vlm\.v\s+v[0-9]+,\s*0\([a-x0-9]+\) +** vsetivli\s+zero,4,e8,mf8,tu,mu +** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),zero +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+,v0.t +** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ +** ret +*/ +void f6 (void * in, void * in2, void *out) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4); + vint8mf8_t v = __riscv_vluxei8_v_i8mf8 (in, index, 4); + vint8mf8_t v2 = __riscv_vluxei8_v_i8mf8_tumu (mask, v, in, index, 4); + __riscv_vsoxei8_v_i8mf8 (out, index, v2, 4); +}