From patchwork Sun Jan 29 15:34:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 1733594 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4P4b3t523vz23dQ for ; Mon, 30 Jan 2023 02:35:22 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 75B333858428 for ; Sun, 29 Jan 2023 15:35:19 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id 519E03858D32 for ; Sun, 29 Jan 2023 15:35:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 519E03858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp82t1675006499t1qp7dkj Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Sun, 29 Jan 2023 23:34:59 +0800 (CST) X-QQ-SSF: 01400000002000E0L000B00A0000000 X-QQ-FEAT: +ynUkgUhZJmvoSKiYlcWVri0/Y6ysOFL+Dq0wBObTlgBNcElGCvC3Xh+R5snT ikJcfD1PpS33VCXu0aPODClXf2NbYUlkyeP+nOgD6mZL/o1MwOVMhLA42eLeS/SpxTm1dQf YD/gu1q2QRJxGhpdpyx7Gj0VFhE128BWD5qC6PViGMsLkHNJC07D1A6oU9CTxqyivRerPAG UlI9+5HqhyVG5eF3jHZME2UJJmNjQ7mvw0OWM60R5UP5daW1FyJC04LSgS+bua+CJIoYyLC LdCNWVMymMRyWpjbnjahvyMIQfsvwMWxsZ2HnwLr/KZkCLZTCddDJ7qEw7vhqcqt2aIrjOC MpyDElB5W/o8IgXFu2wCDEQilhZ7ksa1RJDXnff+ofLuxFrtVFkqWe9LNbHnHfKiWXJ/533 vgz6jQvUDFE= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add VSETVL testcases for indexed loads/stores. Date: Sun, 29 Jan 2023 23:34:57 +0800 Message-Id: <20230129153457.220337-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/avl_single-72.c: New test. * gcc.target/riscv/rvv/vsetvl/avl_single-76.c: New test. * gcc.target/riscv/rvv/vsetvl/avl_single-77.c: New test. --- .../riscv/rvv/vsetvl/avl_single-72.c | 27 +++++++++++++++++++ .../riscv/rvv/vsetvl/avl_single-76.c | 24 +++++++++++++++++ .../riscv/rvv/vsetvl/avl_single-77.c | 27 +++++++++++++++++++ 3 files changed, 78 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c new file mode 100644 index 00000000000..b1e28abd4fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +void f (void * restrict in, void * restrict out, int n, int cond) +{ + size_t vl = 101; + for (size_t i = 0; i < n; i++) + { + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); + __riscv_vse8_v_i8mf8 (out + i, v, vl); + + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl); + __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl); + } + + for (size_t i = 0; i < n; i++) + { + vuint8mf8_t index = __riscv_vle8_v_u8mf8 (in + i + 300, vl); + vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2 (in + i + 200, index, vl); + __riscv_vse32_v_f32mf2 (out + i + 200, v2, vl); + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c new file mode 100644 index 00000000000..1b6e818d209 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +void f (void * restrict in, void * restrict out, int n, int cond) +{ + size_t vl = 101; + for (size_t i = 0; i < n; i++) + { + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); + __riscv_vse8_v_i8mf8 (out + i, v, vl); + } + + for (size_t i = 0; i < n; i++) + { + vuint8mf8_t index = __riscv_vle8_v_u8mf8 (in + i + 300, vl); + vfloat32mf2_t v = __riscv_vle32_v_f32mf2 (in + i + 600, vl); + __riscv_vsoxei8_v_f32mf2 (out + i + 200, index, v, vl); + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c new file mode 100644 index 00000000000..9fb16052385 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +void f (void * restrict in, void * restrict out, int n, int cond) +{ + size_t vl = 101; + for (size_t i = 0; i < n; i++) + { + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); + __riscv_vse8_v_i8mf8 (out + i, v, vl); + } + + for (size_t i = 0; i < n; i++) + { + vbool64_t mask = __riscv_vlm_v_b64 (in + 10000, vl); + vuint8mf8_t index = __riscv_vle8_v_u8mf8 (in + i + 300, vl); + vfloat32mf2_t v = __riscv_vle32_v_f32mf2 (in + i + 30000, vl); + vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2_tumu (mask, v, in + i + 200, index, vl); + __riscv_vse32_v_f32mf2 (out + i + 200, v2, vl); + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +