| Message ID | 20230127123020.260769-1-juzhe.zhong@rivai.ai |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Fix testcases check. | expand |
committed, thanks! On Fri, Jan 27, 2023 at 8:30 PM <juzhe.zhong@rivai.ai> wrote: > From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai> > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Fix testcase check. > * gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Ditto. > * gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Ditto. > > --- > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c | 2 +- > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c | 2 +- > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c | 3 ++- > 3 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c > index e855f86b9a3..2e1f68f9bdc 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c > @@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int l, > int n, int m, int cond) > } > } > > -/* { dg-final { scan-assembler-times > {add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts > "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler > {add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} > { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts > "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c > index 316a4ce6193..a3dca3834e3 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c > @@ -36,4 +36,4 @@ void f (void * restrict in, void * restrict out, int l, > int n, int m, int cond) > } > } > > -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" > no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler > {add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} > { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts > "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c > index df4fdf24a4a..7ad277e0266 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c > @@ -16,4 +16,5 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t m, > size_t n) { > } > } > > -/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0" > no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { > no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]} { target { > no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > -- > 2.36.3 > >
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c index e855f86b9a3..2e1f68f9bdc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c @@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int l, int n, int m, int cond) } } -/* { dg-final { scan-assembler-times {add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler {add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c index 316a4ce6193..a3dca3834e3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c @@ -36,4 +36,4 @@ void f (void * restrict in, void * restrict out, int l, int n, int m, int cond) } } -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler {add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c index df4fdf24a4a..7ad277e0266 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c @@ -16,4 +16,5 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t n) { } } -/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai> gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Fix testcase check. * gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Ditto. --- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c | 3 ++- 3 files changed, 4 insertions(+), 3 deletions(-)