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RISC-V: Clang-format some annotations[NFC]

Message ID 20230118025832.66827-1-juzhe.zhong@rivai.ai
State New
Headers show
Series RISC-V: Clang-format some annotations[NFC] | expand

Commit Message

juzhe.zhong@rivai.ai Jan. 18, 2023, 2:58 a.m. UTC 
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

        * config/riscv/riscv-vsetvl.cc: Clang-format.
---
 gcc/config/riscv/riscv-vsetvl.cc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Jeff Law Jan. 22, 2023, 7:36 p.m. UTC | #1 
On 1/17/23 19:58, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> gcc/ChangeLog:
> 
>          * config/riscv/riscv-vsetvl.cc: Clang-format.
OK.
jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index c2a8b44584d..26d096ea939 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -33,7 +33,8 @@  along with GCC; see the file COPYING3.  If not see
 
     Assumption:
 
-    -  Each avl operand is either an immediate (must be in range 0 ~ 31) or reg.
+    -  Each avl operand is either an immediate (must be in range 0 ~ 31) or
+   reg.
 
     This pass consists of 5 phases:
 
@@ -43,7 +44,8 @@  along with GCC; see the file COPYING3.  If not see
     -  Phase 2 - Emit vsetvl instructions within each basic block according to
        demand, compute and save ANTLOC && AVLOC of each block.
 
-    -  Phase 3 - Backward && forward demanded info propagation and fusion across blocks.
+    -  Phase 3 - Backward && forward demanded info propagation and fusion
+   across blocks.
 
     -  Phase 4 - Lazy code motion including: compute local properties,
        pre_edge_lcm and vsetvl insertion && delete edges for LCM results.