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From: juzhe.zhong@rivai.ai
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com,
 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Subject: [PATCH] RISC-V: Add testcases for AVL=REG support
Date: Tue, 10 Jan 2023 07:38:38 +0800
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From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/vsetvl/avl_single-2.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-20.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-21.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-22.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-23.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-24.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-25.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-26.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-27.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-28.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-29.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-3.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-30.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-31.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-32.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-33.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-34.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-35.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-36.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-37.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-38.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-39.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-4.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-40.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-41.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-42.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-43.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-44.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-45.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-46.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-47.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-48.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-49.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-5.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-50.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-51.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-52.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-53.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-54.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-55.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-56.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-57.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-58.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-59.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-6.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-60.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-61.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-62.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-63.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-64.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-65.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-66.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-67.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-68.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-69.c: New test.
---
 .../riscv/rvv/vsetvl/avl_single-2.c           | 18 ++++++
 .../riscv/rvv/vsetvl/avl_single-20.c          | 40 +++++++++++++
 .../riscv/rvv/vsetvl/avl_single-21.c          | 32 +++++++++++
 .../riscv/rvv/vsetvl/avl_single-22.c          | 42 ++++++++++++++
 .../riscv/rvv/vsetvl/avl_single-23.c          | 34 +++++++++++
 .../riscv/rvv/vsetvl/avl_single-24.c          | 36 ++++++++++++
 .../riscv/rvv/vsetvl/avl_single-25.c          | 38 +++++++++++++
 .../riscv/rvv/vsetvl/avl_single-26.c          | 35 ++++++++++++
 .../riscv/rvv/vsetvl/avl_single-27.c          | 36 ++++++++++++
 .../riscv/rvv/vsetvl/avl_single-28.c          | 30 ++++++++++
 .../riscv/rvv/vsetvl/avl_single-29.c          | 31 ++++++++++
 .../riscv/rvv/vsetvl/avl_single-3.c           | 19 +++++++
 .../riscv/rvv/vsetvl/avl_single-30.c          | 29 ++++++++++
 .../riscv/rvv/vsetvl/avl_single-31.c          | 27 +++++++++
 .../riscv/rvv/vsetvl/avl_single-32.c          | 27 +++++++++
 .../riscv/rvv/vsetvl/avl_single-33.c          | 29 ++++++++++
 .../riscv/rvv/vsetvl/avl_single-34.c          | 28 +++++++++
 .../riscv/rvv/vsetvl/avl_single-35.c          | 27 +++++++++
 .../riscv/rvv/vsetvl/avl_single-36.c          | 25 ++++++++
 .../riscv/rvv/vsetvl/avl_single-37.c          | 29 ++++++++++
 .../riscv/rvv/vsetvl/avl_single-38.c          | 57 +++++++++++++++++++
 .../riscv/rvv/vsetvl/avl_single-39.c          | 19 +++++++
 .../riscv/rvv/vsetvl/avl_single-4.c           | 21 +++++++
 .../riscv/rvv/vsetvl/avl_single-40.c          | 17 ++++++
 .../riscv/rvv/vsetvl/avl_single-41.c          | 19 +++++++
 .../riscv/rvv/vsetvl/avl_single-42.c          | 15 +++++
 .../riscv/rvv/vsetvl/avl_single-43.c          | 16 ++++++
 .../riscv/rvv/vsetvl/avl_single-44.c          | 19 +++++++
 .../riscv/rvv/vsetvl/avl_single-45.c          | 19 +++++++
 .../riscv/rvv/vsetvl/avl_single-46.c          | 25 ++++++++
 .../riscv/rvv/vsetvl/avl_single-47.c          | 35 ++++++++++++
 .../riscv/rvv/vsetvl/avl_single-48.c          | 32 +++++++++++
 .../riscv/rvv/vsetvl/avl_single-49.c          | 32 +++++++++++
 .../riscv/rvv/vsetvl/avl_single-5.c           | 18 ++++++
 .../riscv/rvv/vsetvl/avl_single-50.c          | 23 ++++++++
 .../riscv/rvv/vsetvl/avl_single-51.c          | 25 ++++++++
 .../riscv/rvv/vsetvl/avl_single-52.c          | 34 +++++++++++
 .../riscv/rvv/vsetvl/avl_single-53.c          | 31 ++++++++++
 .../riscv/rvv/vsetvl/avl_single-54.c          | 32 +++++++++++
 .../riscv/rvv/vsetvl/avl_single-55.c          | 38 +++++++++++++
 .../riscv/rvv/vsetvl/avl_single-56.c          | 38 +++++++++++++
 .../riscv/rvv/vsetvl/avl_single-57.c          | 43 ++++++++++++++
 .../riscv/rvv/vsetvl/avl_single-58.c          | 43 ++++++++++++++
 .../riscv/rvv/vsetvl/avl_single-59.c          | 31 ++++++++++
 .../riscv/rvv/vsetvl/avl_single-6.c           | 22 +++++++
 .../riscv/rvv/vsetvl/avl_single-60.c          | 30 ++++++++++
 .../riscv/rvv/vsetvl/avl_single-61.c          | 24 ++++++++
 .../riscv/rvv/vsetvl/avl_single-62.c          | 24 ++++++++
 .../riscv/rvv/vsetvl/avl_single-63.c          | 24 ++++++++
 .../riscv/rvv/vsetvl/avl_single-64.c          | 41 +++++++++++++
 .../riscv/rvv/vsetvl/avl_single-65.c          | 33 +++++++++++
 .../riscv/rvv/vsetvl/avl_single-66.c          | 21 +++++++
 .../riscv/rvv/vsetvl/avl_single-67.c          | 26 +++++++++
 .../riscv/rvv/vsetvl/avl_single-68.c          | 25 ++++++++
 .../riscv/rvv/vsetvl/avl_single-69.c          | 40 +++++++++++++
 55 files changed, 1604 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c
new file mode 100644
index 00000000000..aefb107d0e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, size_t vl)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl << 3);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl << 3);
+    }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {slli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c
new file mode 100644
index 00000000000..cda2e0ea2f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond)
+{
+  size_t vl = 101;
+  vbool64_t mask = *(vbool64_t*) (in + 1000000);
+  for (size_t j = 0; j < m; j++){
+    for (size_t i = 0; i < cond; i++)
+      {
+        vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
+        __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      }
+
+    for (size_t i = 0; i < n * n; i++)
+      out[i] = out[i] * out[i];
+    for (size_t i = 0; i < n * n * n; i++)
+      out[i] = out[i] + out[i];
+    for (size_t i = 0; i < n * n * n * n; i++)
+      out[i] = out[i] + 2;
+    for (size_t i = 0; i < n * n * n * n * n; i++)
+      out[i] = out[i] * 100;
+    for (size_t i = 0; i < n * n * n * n * n * n; i++)
+      out[i] = out[i] - 77;
+  
+    for (size_t i = 0; i < n; i++)
+      {
+        vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j + 200), vl);
+        __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl);
+        
+        vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + j + 300), vl);
+        __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + j + 300), v2, vl);
+      }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c
new file mode 100644
index 00000000000..d8f114c614d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond)
+{
+  size_t vl = 101;
+  vbool64_t mask = *(vbool64_t*) (in + 1000000);
+  for (size_t j = 0; j < m; j++){
+
+    if (cond) {
+      for (size_t i = 0; i < n; i++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i, v, vl);
+        }
+    } else {
+      for (size_t i = 0; i < n; i++)
+        {
+          vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j + 200), vl);
+          __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl);
+          
+          vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + j + 300), vl);
+          __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + j + 300), v2, vl);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c
new file mode 100644
index 00000000000..d5e5f5a8dd5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond)
+{
+  vbool64_t mask = *(vbool64_t*) (in + 1000000);
+  for (size_t j = 0; j < m; j++){
+    
+    size_t vl = 101;
+    for (size_t i = 0; i < n; i++)
+      {
+        vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
+        __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      }
+
+    for (size_t i = 0; i < n * n; i++)
+      out[i] = out[i] * out[i];
+    for (size_t i = 0; i < n * n * n; i++)
+      out[i] = out[i] + out[i];
+    for (size_t i = 0; i < n * n * n * n; i++)
+      out[i] = out[i] + 2;
+    for (size_t i = 0; i < n * n * n * n * n; i++)
+      out[i] = out[i] * 100;
+    for (size_t i = 0; i < n * n * n * n * n * n; i++)
+      out[i] = out[i] - 77;
+    
+    vl = 101;
+    for (size_t i = 0; i < n; i++)
+      {
+        vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j + 200), vl);
+        __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl);
+        
+        vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + j + 300), vl);
+        __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + j + 300), v2, vl);
+      }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
new file mode 100644
index 00000000000..aa10b7724fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond)
+{
+  vbool64_t mask = *(vbool64_t*) (in + 1000000);
+  for (size_t j = 0; j < m; j++){
+    
+    size_t vl = 101;
+    for (size_t i = 0; i < n; i++)
+      {
+        vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
+        __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      }
+
+    vl = 102;
+    for (size_t i = 0; i < n; i++)
+      {
+        vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j + 200), vl);
+        __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl);
+        
+        vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + j + 300), vl);
+        __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + j + 300), v2, vl);
+      }
+  }
+}
+
+/* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,101} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,102} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c
new file mode 100644
index 00000000000..2fd09649c0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond)
+{
+  vbool64_t mask = *(vbool64_t*) (in + 1000000);
+  for (size_t j = 0; j < m; j++){
+    
+    size_t vl = 101;
+    for (size_t i = 0; i < n; i++)
+      {
+        vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
+        __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      }
+
+    for (size_t i = 0; i < cond; i++)
+      out[i] = out[i] * out[i];
+    
+    vl = 102;
+    for (size_t i = 0; i < n; i++)
+      {
+        vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j + 200), vl);
+        __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl);
+        
+        vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + j + 300), vl);
+        __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + j + 300), v2, vl);
+      }
+  }
+}
+
+/* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,101} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,102} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c
new file mode 100644
index 00000000000..cfb7d789758
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond)
+{
+  vbool64_t mask = *(vbool64_t*) (in + 1000000);
+  size_t vl = 101;
+  for (size_t j = 0; j < m; j++){
+
+    if (cond) {
+      for (size_t i = 0; i < n; i++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i, v, vl);
+        }
+    } else {
+      for (size_t i = 0; i < n; i++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + 100, vl);
+          __riscv_vse8_v_i8mf8 (out + i + 100, v, vl);
+        }
+    }
+    
+    for (size_t i = 0; i < n; i++)
+      {
+        vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j + 200), vl);
+        __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl);
+        
+        vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + j + 300), vl);
+        __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + j + 300), v2, vl);
+      }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c
new file mode 100644
index 00000000000..13eee2157e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond)
+{
+  vbool64_t mask = *(vbool64_t*) (in + 1000000);
+  size_t vl = 101;
+  for (size_t j = 0; j < m; j++){
+
+    if (cond) {
+      for (size_t i = 0; i < n; i++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i, v, vl);
+        }
+    } else {
+      for (size_t i = 0; i < cond; i++)
+        out[i] = out[i] * 33;
+    }
+    
+    for (size_t i = 0; i < n; i++)
+      {
+        vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j + 200), vl);
+        __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl);
+        
+        vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + j + 300), vl);
+        __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + j + 300), v2, vl);
+      }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c
new file mode 100644
index 00000000000..179fccd237c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned cond, size_t vl)
+{
+  vbool64_t mask = *(vbool64_t*) (in + 1000000);
+
+  vl = 101;
+  if (cond > 0) {
+    for (size_t i = 0; i < n; i++)
+      {
+        vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+        __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      }
+  } else {
+    for (size_t i = 0; i < n; i++)
+      {
+        vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 1000, vl);
+        __riscv_vse8_v_i8mf8 (out + i + 1000, v, vl);
+      }
+  }
+    
+  for (size_t i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + 200), vl);
+      __riscv_vse32_v_f32mf2 ((float *)(out + i + 200), v, vl);
+      
+      vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + 300), vl);
+      __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + 300), v2, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c
new file mode 100644
index 00000000000..b5b3fda1bab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned cond, size_t vl)
+{
+  vbool64_t mask = *(vbool64_t*) (in + 1000000);
+
+  vl = 101;
+  if (cond > 0) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, vl);
+    __riscv_vse8_v_i8mf8 (out, v, vl);
+  } else {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 10000, vl);
+    __riscv_vse8_v_i8mf8 (out + 10000, v, vl);
+  }
+    
+  for (size_t i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + 200), vl);
+      __riscv_vse32_v_f32mf2 ((float *)(out + i + 200), v, vl);
+      
+      vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + 300), vl);
+      __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + 300), v2, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c
new file mode 100644
index 00000000000..f6296e0af93
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned cond, size_t vl)
+{
+  vbool64_t mask = *(vbool64_t*) (in + 1000000);
+
+  vl = 101;
+  if (cond > 0) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, vl);
+    __riscv_vse8_v_i8mf8 (out, v, vl);
+  } else {
+    vint16mf4_t v = __riscv_vle16_v_i16mf4 ((int16_t *)(in + 10000), vl);
+    __riscv_vse16_v_i16mf4 ((int16_t *)(out + 10000), v, vl);
+  }
+    
+  for (size_t i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + 200), vl);
+      __riscv_vse32_v_f32mf2 ((float *)(out + i + 200), v, vl);
+      
+      vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + 300), vl);
+      __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + 300), v2, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c
new file mode 100644
index 00000000000..68505ca258c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, size_t vl)
+{
+  vl = vl << 3;
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {slli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c
new file mode 100644
index 00000000000..be5986e00a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned cond, size_t vl)
+{
+  vbool64_t mask = *(vbool64_t*) (in + 1000000);
+
+  vl = 101;
+  if (cond > 0) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, vl);
+    __riscv_vse8_v_i8mf8 (out, v, vl);
+  } else {
+    out[100] = out[100] + 300;
+  }
+    
+  for (size_t i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + 200), vl);
+      __riscv_vse32_v_f32mf2 ((float *)(out + i + 200), v, vl);
+      
+      vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + 300), vl);
+      __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + 300), v2, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c
new file mode 100644
index 00000000000..9afa5470b3c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  size_t vl = *(size_t*)(in + 10000);
+  
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 300, v, vl);
+    }
+
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c
new file mode 100644
index 00000000000..31363d2624d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  size_t vl = ((cond + 100) * cond) >> 3;
+  
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 300, v, vl);
+    }
+  
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c
new file mode 100644
index 00000000000..f4f58cd2c3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+char fn3 (void);
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  size_t vl = fn3 ();
+  
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 300, v, vl);
+    }
+  
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c
new file mode 100644
index 00000000000..d28c12bdd49
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  size_t vl;
+  asm volatile ("li %0, 101" :"=r" (vl)::"memory");
+  
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 300, v, vl);
+    }
+  
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c
new file mode 100644
index 00000000000..28230914cf7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+static int vl = 0x5545515;
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 300, v, vl);
+    }
+  
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c
new file mode 100644
index 00000000000..3c93675a32d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300,555);
+      __riscv_vse8_v_i8mf8 (out + i + 300, v,555);
+    }
+
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i,555);
+      __riscv_vse8_v_i8mf8 (out + i, v,555);
+      
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100,555);
+      __riscv_vse8_v_i8mf8 (out + i + 100, v2,555);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c
new file mode 100644
index 00000000000..0c6a25170cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned cond, size_t vl)
+{
+  asm volatile ("li %0, 101" :"=r" (vl)::"memory");
+  vbool64_t mask = *(vbool64_t*) (in + 1000000);
+  if (cond > 0) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, vl);
+    __riscv_vse8_v_i8mf8 (out, v, vl);
+  } else {
+    out[100] = out[100] + 300;
+  }
+    
+  for (size_t i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + 200), vl);
+      __riscv_vse32_v_f32mf2 ((float *)(out + i + 200), v, vl);
+      
+      vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + 300), vl);
+      __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + 300), v2, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+addi\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[0-9]00\s+addi\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[0-9]00\s+addi\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[0-9]00\s+add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c
new file mode 100644
index 00000000000..ba90e79fbf5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int8_t * restrict out2, int n, int m, unsigned cond, size_t vl)
+{
+  vl = 22;
+  vbool64_t mask = *(vbool64_t*) (in + 1000000);
+  if (cond == 0) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, vl);
+    __riscv_vse8_v_i8mf8 (out, v, vl);
+  } else {
+    out2[100] = out2[100] + 300;
+  }
+
+  for (size_t i = 0; i < n; i++)
+    out[i + 200] = out[i + 500] + 22;
+
+  for (size_t i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + 200), 22);
+      __riscv_vse32_v_f32mf2 ((float *)(out + i + 200), v, 22);
+      
+      vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + 300), 22);
+      __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + 300), v2, 22);
+    }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned cond, size_t vl)
+{
+  asm volatile ("li %0, 101" :"=r" (vl)::"memory");
+  vbool64_t mask = *(vbool64_t*) (in + 1000000);
+  if (cond > 0) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, vl);
+    __riscv_vse8_v_i8mf8 (out, v, vl);
+  } else {
+    out[100] = out[100] + 300;
+  }
+
+  for (size_t i = 0; i < n; i++)
+    out[i + 200] = out[i + 500] + 555;
+
+  for (size_t i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + 200), vl);
+      __riscv_vse32_v_f32mf2 ((float *)(out + i + 200), v, vl);
+      
+      vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + 300), vl);
+      __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + 300), v2, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,22,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c
new file mode 100644
index 00000000000..06f57dc6e52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t *base, int8_t *out, size_t m, size_t n) {
+  int vl = 101;
+  for (size_t i = 0; i < m; i++) {
+    vint8mf8_t v0 = __riscv_vle8_v_i8mf8_tu(v0, base + i, vl);
+    if (n > 100) {
+      __riscv_vse8_v_i8mf8(out + i + 100, v0, vl);
+    } else {
+      __riscv_vse8_v_i8mf8(out + i, v0, vl);
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
new file mode 100644
index 00000000000..4fd3ece0e16
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int l, int n, int m, size_t vl)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i + j, v, vl);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c
new file mode 100644
index 00000000000..796b40fe494
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t *base, int8_t *out, size_t m, size_t n) {
+  for (size_t i = 0; i < m; i++) {
+    for (size_t j = 0; j < n; j += 1) {
+      vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, j);
+      v0 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 100, j);
+      __riscv_vse8_v_i8mf8(out + i, v0, j);
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c
new file mode 100644
index 00000000000..0589ebabf6c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t *base, int8_t *out, size_t m, size_t n) {
+  int vl = 101;
+  for (size_t i = 0; i < m; i++) {
+    vint8mf8_t v0 = __riscv_vle8_v_i8mf8_tu(v0, base + i, vl);
+    if (n > 100) {
+      __riscv_vse8_v_i8mf8(out + i + 100, v0, vl);
+    } else {
+      __riscv_vse8_v_i8mf8(out + i, v0, vl);
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c
new file mode 100644
index 00000000000..b5ffcbe9172
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t *base, int8_t *out, size_t m, size_t n) {
+  for (size_t i = 0; i < m; i++) {
+    for (size_t j = 0; j < n; j += 1) {
+      vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, i);
+      v0 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 100, i);
+      __riscv_vse8_v_i8mf8(out + i, v0, i);
+    }
+  }
+}
+/* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c
new file mode 100644
index 00000000000..44488aab2db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(int8_t *base, int8_t *out, size_t vl, size_t m) {
+  vbool64_t mask = *(vbool64_t*) (base + 10000);
+  for (size_t i = 0; i < m; i++) {
+    vint8mf8_t v0 = __riscv_vle8_v_i8mf8_mu(mask, v0, base + i, vl);
+    __riscv_vse8_v_i8mf8(out + i, v0, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\),v0\.t} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c
new file mode 100644
index 00000000000..0f4d60e9adf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(int8_t *base, int8_t *out, size_t vl, size_t m) {
+  vbool64_t mask = *(vbool64_t*) (base + 10000);
+  vint8mf8_t v0;
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      v0 = __riscv_vle8_v_i8mf8_tumu(mask, v0, base + i, vl);
+    } else {
+      __riscv_vse8_v_i8mf8(out + i, v0, vl);
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+j\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c
new file mode 100644
index 00000000000..a2ee5ec4115
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo1_7(int8_t *base, int8_t *out, size_t vl, size_t m, size_t n, size_t o, size_t p) {
+  size_t avl = vl;
+  if (o > p) {
+    for (size_t i = 0; i < m; i++) {
+      vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);
+      v0 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 100, avl);
+      __riscv_vse8_v_i8mf8(out + i, v0, avl);
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c
new file mode 100644
index 00000000000..1c5ee6a60cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  int vl = 101;
+  if (n > cond) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 600, vl);
+    vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + 600, vl);
+    __riscv_vse8_v_i8mf8 (out + 600, v2, vl);
+  } else {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 700, vl);
+    __riscv_vse8_v_i8mf8 (out + 700, v, vl);
+  }
+
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 900 + i, vl);
+    __riscv_vse8_v_i8mf8 (out + 900 + i, v, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c
new file mode 100644
index 00000000000..15ecb5d171a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  size_t vl;
+  asm volatile ("li %0, 101" :"=r" (vl)::"memory");
+  if (n > cond) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 600, cond);
+    vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + 600, cond);
+    __riscv_vse8_v_i8mf8 (out + 600, v2, cond);
+  } else {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 700, cond);
+    __riscv_vse8_v_i8mf8 (out + 700, v, cond);
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 900 + i, cond);
+    __riscv_vse8_v_i8mf8 (out + 900 + i, v, cond);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c
new file mode 100644
index 00000000000..319db5442f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int n2)
+{
+  size_t vl;
+  asm volatile ("li %0, 101" :"=r" (vl)::"memory");
+  for (int i = 0 ; i < n2; i++) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 800 + i, vl);
+    v = __riscv_vle8_v_i8mf8_tu (v, in + 900 + i, vl);
+    __riscv_vse8_v_i8mf8 (out + 800 + i, v, vl);
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 900 + i, vl);
+    __riscv_vse8_v_i8mf8 (out + 900 + i, v, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c
new file mode 100644
index 00000000000..4fa68627cc0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int n2)
+{
+  size_t vl;
+  asm volatile ("li %0, 101" :"=r" (vl)::"memory");
+  for (int i = 0 ; i < n2; i++) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 800 + i, vl);
+    __riscv_vse8_v_i8mf8 (out + 800 + i, v, vl);
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  asm volatile ("li %0, 102" :"=r" (vl)::"memory");
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 900 + i, vl);
+    __riscv_vse8_v_i8mf8 (out + 900 + i, v, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c
new file mode 100644
index 00000000000..9980242b591
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int vl)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      vl++;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c
new file mode 100644
index 00000000000..d91d2e0005c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, size_t m) {
+  vbool64_t mask = *(vbool64_t*)mask_in;
+  size_t vl = 105;
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, vl);
+      vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 100, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v1, vl);
+    } else {
+      vint16mf4_t v0 = __riscv_vle16_v_i16mf4(base + i, vl);
+      vint16mf4_t v1 = __riscv_vle16_v_i16mf4_mu(mask, v0, base + i + 100, vl);
+      __riscv_vse16_v_i16mf4 (out + i, v1, vl);
+    }
+  }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c
new file mode 100644
index 00000000000..0cb55ba28c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, size_t m, size_t n) {
+  vbool64_t mask = *(vbool64_t*)mask_in;
+  size_t vl = 106;
+  for (size_t i = 0; i < m; i++) {
+    for (size_t j = 0; j < n; j++){
+      if ((i + j) % 2 == 0) {
+        vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j, vl);
+        vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + j + 100, vl);
+        __riscv_vse8_v_i8mf8 (out + i + j, v1, vl);
+      } else {
+        vint16mf4_t v0 = __riscv_vle16_v_i16mf4(base + i + j, vl);
+        vint16mf4_t v1 = __riscv_vle16_v_i16mf4_mu(mask, v0, base + i + j + 100, vl);
+        __riscv_vse16_v_i16mf4 (out + i + j, v1, vl);
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c
new file mode 100644
index 00000000000..882576e30d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, size_t m, size_t n) {
+  
+  size_t vl = 107;
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j + 700, vl);
+        vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + j + 700, vl);
+        __riscv_vse8_v_i8mf8 (out + i + j + 700, v1, vl);
+        if (j % 2 == 0) {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j + 500, vl);
+          __riscv_vse8_v_i8mf8 (out + i + j + 500, v0, vl);
+        } else {
+          vint16mf4_t v0 = __riscv_vle16_v_i16mf4(base + i + j + 600, vl);
+          __riscv_vse16_v_i16mf4 (out + i + j + 600, v0, vl);
+        }
+      }
+    } else {
+      for (size_t j = 0; j < n; j++){
+        vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j + 200, vl);
+        vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + j + 300, vl);
+        __riscv_vse8_v_i8mf8 (out + i + j + 400, v1, vl);
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c
new file mode 100644
index 00000000000..dbdb025986e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, size_t m, size_t n) {
+
+  size_t vl = 222;
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j + 500, vl);
+          __riscv_vse8_v_i8mf8 (out + i + j + 500, v0, vl);
+        } else {
+          vint16mf4_t v0 = __riscv_vle16_v_i16mf4(base + i + j + 600, vl);
+          __riscv_vse16_v_i16mf4 (out + i + j + 600, v0, vl);
+        }
+      }
+    } else {
+      for (size_t j = 0; j < n; j++){
+        vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j + 200, vl);
+        vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + j + 300, vl);
+        __riscv_vse8_v_i8mf8 (out + i + j + 400, v1, vl);
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c
new file mode 100644
index 00000000000..7b85cc7072f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, size_t m, size_t n) {
+  
+  size_t vl = 333;
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 200, vl);
+          vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 200, vl);
+          __riscv_vse8_v_i8mf8 (out + i + 200, v1, vl);
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 300, vl);
+          vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 300, vl);
+          __riscv_vse8_v_i8mf8 (out + i + 300, v1, vl);
+        }
+      }
+    } else {
+      for (size_t j = 0; j < n; j++){
+        vint8mf8_t v1 = __riscv_vle8_v_i8mf8(base + i + j + 300, vl);
+        __riscv_vse8_v_i8mf8 (out + i + j + 400, v1, vl);
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c
new file mode 100644
index 00000000000..6c7aeea5f34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, size_t m, size_t n) {
+  
+  size_t vl = 444;
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 200 + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i + 200, v0, vl);
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 300 + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i + 300, v0, vl);
+        }
+      }
+    } else {
+      for (size_t j = 0; j < vl; j++){
+        if (j % 2 == 0) {
+          for (size_t k = 0; k < n; k++) {
+            vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 500 + k + j, vl);
+            vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 600 + k + j, vl);
+            __riscv_vse8_v_i8mf8 (out + i + 600, v1, vl);
+          }
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 700, vl);
+          __riscv_vse8_v_i8mf8 (out + i + 800, v0, vl);
+        }
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c
new file mode 100644
index 00000000000..5d0584e981f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, size_t m, size_t n) {
+  
+  size_t vl = 555;
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 200 + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i + 200, v0, vl);
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 300 + j, vl);
+          vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 300 + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i + 300, v1, vl);
+        }
+      }
+    } else {
+      for (size_t j = 0; j < vl; j++){
+        if (j % 2 == 0) {
+          for (size_t k = 0; k < n; k++) {
+            vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 500 + k + j, vl);
+            __riscv_vse8_v_i8mf8 (out + i + 600, v0, vl);
+          }
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 700, vl);
+          __riscv_vse8_v_i8mf8 (out + i + 800, v0, vl);
+        }
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c
new file mode 100644
index 00000000000..a41065b5710
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, 
+size_t m, size_t n, size_t a, size_t b) {
+  
+  size_t vl = 666;
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 200 + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i + 200, v0, vl);
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 300 + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i + 300, v0, vl);
+        }
+      }
+    } else {
+      for (size_t j = 0; j < vl; j++){
+        if (j % 2 == 0) {
+          for (size_t k = 0; k < n; k++) {
+            for (size_t i_a = 0; i_a < a; i_a++){
+              for (size_t i_b = 0; i_b < b; i_b++){
+                vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 500 + k + j + i_a + i_b, vl);
+                vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 600 + k + j + i_a + i_b, vl);
+                __riscv_vse8_v_i8mf8 (out + i + 600 + j + k + i_a + i_b, v1, vl);
+              }
+            }
+          }
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 700, vl);
+          __riscv_vse8_v_i8mf8 (out + i + 800, v0, vl);
+        }
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c
new file mode 100644
index 00000000000..610b731aaba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, 
+size_t m, size_t n, size_t a, size_t b) {
+  
+  size_t vl = 345;
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          for (size_t k = 0; k < n; k++) {
+            for (size_t i_a = 0; i_a < a; i_a++){
+              for (size_t i_b = 0; i_b < b; i_b++){
+                vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 500 + k + j + i_a + i_b, vl);
+                vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 600 + k + j + i_a + i_b, vl);
+                __riscv_vse8_v_i8mf8 (out + i + 600 + j + k + i_a + i_b, v1, vl);
+              }
+            }
+          }
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 300 + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i + 300, v0, vl);
+        }
+      }
+    } else {
+      for (size_t j = 0; j < vl; j++){
+        if (j % 2 == 0) {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 200 + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i + 200, v0, vl);
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 700, vl);
+          __riscv_vse8_v_i8mf8 (out + i + 800, v0, vl);
+        }
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c
new file mode 100644
index 00000000000..82b82aed983
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, 
+size_t m, size_t n, size_t a, size_t b) {
+
+  size_t vl = 99;
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          for (size_t k = 0; k < n; k++) {
+            for (size_t i_a = 0; i_a < a; i_a++){
+              for (size_t i_b = 0; i_b < b; i_b++){
+                vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 500 + k + j + i_a + i_b, vl);
+                vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 600 + k + j + i_a + i_b, vl);
+                __riscv_vse8_v_i8mf8 (out + i + 600 + j + k + i_a + i_b, v1, vl);
+              }
+            }
+          }
+        } else {
+        }
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
new file mode 100644
index 00000000000..02f62b46b20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int l, int n, int m, size_t vl)
+{
+  for (int i = 0; i < l; i++){
+    vl++;
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k, vl);
+          __riscv_vse8_v_i8mf8 (out + i + j + k, v, vl);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+ble\s+[a-x0-9]+,\s*zero,\.L[0-9]+\s+\.L[0-9]+\:\s+add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c
new file mode 100644
index 00000000000..731184d5e4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, 
+size_t m, size_t n, size_t a, size_t b) {
+  
+  size_t vl = 999;
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          for (size_t k = 0; k < n; k++) {
+            for (size_t i_a = 0; i_a < a; i_a++){
+              for (size_t i_b = 0; i_b < b; i_b++){
+                vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 500 + k + j + i_a + i_b, vl);
+                vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 600 + k + j + i_a + i_b, vl);
+                __riscv_vse8_v_i8mf8 (out + i + 600 + j + k + i_a + i_b, v1, vl);
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c
new file mode 100644
index 00000000000..5e7dabf45a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, size_t n, size_t cond)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i != cond) {
+        size_t vl = 55;
+        vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 100, vl);
+        __riscv_vse8_v_i8mf8 (out + i + 100, v, vl);
+      } else {
+      size_t vl = 66;
+        vint32m1_t v = __riscv_vle32_v_i32m1 (in + i + 200, vl);
+        __riscv_vse32_v_i32m1 (out + i + 200, v, vl);
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c
new file mode 100644
index 00000000000..fbc4d58881b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, size_t n, size_t cond)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i == cond) {
+        size_t vl = 55;
+        vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 100, vl);
+        __riscv_vse8_v_i8mf8 (out + i + 100, v, vl);
+      } else {
+      size_t vl = 66;
+        vint32m1_t v = __riscv_vle32_v_i32m1 (in + i + 200, vl);
+        __riscv_vse32_v_i32m1 (out + i + 200, v, vl);
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c
new file mode 100644
index 00000000000..5433b18cfc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  size_t vl = 111;
+  if (n > cond) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 600, vl);
+    vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + 600, vl);
+    __riscv_vse8_v_i8mf8 (out + 600, v2, vl);
+  } else {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 700, vl);
+    __riscv_vse8_v_i8mf8 (out + 700, v, vl);
+  }
+
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*) (in + 900 + i);
+    *(vint8mf8_t*) (out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c
new file mode 100644
index 00000000000..093f67f6767
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  size_t vl = 777;
+  if (n > cond) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 600, vl);
+    vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + 600, vl);
+    __riscv_vse8_v_i8mf8 (out + 600, v2, vl);
+  } else {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 700, vl);
+    __riscv_vse8_v_i8mf8 (out + 700, v, vl);
+  }
+
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*) (in + 900 + i);
+    *(vint8mf8_t*) (out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n; i++) {
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in + 1000 + i, vl);
+    __riscv_vse32_v_i32m1 (out + 1000 + i, v, vl);
+  }
+  
+  vl = 888;
+  for (int i = 0 ; i < n; i++) {
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in + 1000 + i, vl);
+    __riscv_vse32_v_i32m1 (out + 1000 + i, v, vl);
+  }
+  
+  vl = 444;
+  for (int i = 0 ; i < n * n; i++) {
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in + 2000 + i, vl);
+    __riscv_vse32_v_i32m1 (out + 2000 + i, v, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 6 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c
new file mode 100644
index 00000000000..24d3300ccbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int n2)
+{
+  size_t vl;
+  asm volatile ("li %0, 101" :"=r" (vl)::"memory");
+
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 900 + i, vl);
+    __riscv_vse8_v_i8mf8 (out + 900 + i, v, vl);
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n2; i++) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 800 + i, vl);
+    v = __riscv_vle8_v_i8mf8_tu (v, in + 900 + i, vl);
+    __riscv_vse8_v_i8mf8 (out + 800 + i, v, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
new file mode 100644
index 00000000000..f9073e65ff5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f2 (void * restrict in, void * restrict out, int l, int n, int m, size_t vl)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k, vl);
+          __riscv_vse8_v_i8mf8 (out + i + j + k, v, vl);
+        }
+    }
+    vl++;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+ble\s+[a-x0-9]+,\s*zero,\.L[0-9]+\s+\.L[0-9]+\:\s+add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
new file mode 100644
index 00000000000..3828afa9de8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f2 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  size_t vl = 101;
+  for (int i = 0; i < l; i++){
+    size_t vl = i + vl + 44;
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k + 10000, vl);
+          v = __riscv_vle8_v_i8mf8_tu (v, in + i + j + k + 20000, j);
+          __riscv_vse8_v_i8mf8 (out + i + j + k + 20000, v, vl);
+        }
+    }
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+    __riscv_vse8_v_i8mf8 (out + i, v, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
new file mode 100644
index 00000000000..71071729048
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f2 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  size_t vl = 101;
+  for (int i = 0; i < l; i++){
+    size_t vl = i + vl + 44;
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k + 10000, vl);
+          v = __riscv_vle8_v_i8mf8_tu (v, in + i + j + k + 20000, vl);
+          __riscv_vse8_v_i8mf8 (out + i + j + k + 20000, v, vl);
+        }
+    }
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+    __riscv_vse8_v_i8mf8 (out + i, v, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c
new file mode 100644
index 00000000000..81699d7123d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int l, int n, int m, size_t cond)
+{
+  size_t vl = 555;
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k, vl);
+          __riscv_vse8_v_i8mf8 (out + i + j + k, v, vl);
+        }
+    }
+  }
+  
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          out[i+j+k+10000000] = out[i+j+k+10000000] + in[i+j+k+10000000];
+        }
+    }
+  }
+
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k + 10000, vl);
+          __riscv_vse8_v_i8mf8 (out + i + j + k + 10000, v, vl);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */