diff mbox series

RISC-V: optimize '(a >= 0) ? b : 0' to srai + andn, if compiling for Zbb

Message ID 20221108195456.2701279-1-philipp.tomsich@vrull.eu
State New
Headers show
Series RISC-V: optimize '(a >= 0) ? b : 0' to srai + andn, if compiling for Zbb | expand

Commit Message

Philipp Tomsich Nov. 8, 2022, 7:54 p.m. UTC 
If-conversion is turning '(a >= 0) ? b : 0' into a branchless sequence
	not	a5,a0
	srai	a5,a5,63
	and	a0,a1,a5
missing the opportunity to combine the NOT and AND into an ANDN.

This adds a define_split to help the combiner reassociate the NOT with
the AND.


gcc/ChangeLog:

	* config/riscv/bitmanip.md: New define_split.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zbb-srai-andn.c: New test.

---

 gcc/config/riscv/bitmanip.md                   | 13 +++++++++++++
 gcc/testsuite/gcc.target/riscv/zbb-srai-andn.c | 15 +++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-srai-andn.c

Comments

Jeff Law Nov. 13, 2022, 12:24 a.m. UTC | #1 
On 11/8/22 12:54, Philipp Tomsich wrote:
> If-conversion is turning '(a >= 0) ? b : 0' into a branchless sequence
> 	not	a5,a0
> 	srai	a5,a5,63
> 	and	a0,a1,a5
> missing the opportunity to combine the NOT and AND into an ANDN.
>
> This adds a define_split to help the combiner reassociate the NOT with
> the AND.
>
>
> gcc/ChangeLog:
>
> 	* config/riscv/bitmanip.md: New define_split.
>
> gcc/testsuite/ChangeLog:
>
> 	* gcc.target/riscv/zbb-srai-andn.c: New test.

OK.


FWIW, combine can be pretty sneaky in manipulating the result of a scc 
style insn.    I've seen a port with pages and pages of special patterns 
to match what simplify_if_then_else would do.


Jeff
Philipp Tomsich Nov. 13, 2022, 3:48 p.m. UTC | #2 
Applied to master. Thanks!
--Philipp.

On Sun, 13 Nov 2022 at 01:24, Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
> On 11/8/22 12:54, Philipp Tomsich wrote:
> > If-conversion is turning '(a >= 0) ? b : 0' into a branchless sequence
> >       not     a5,a0
> >       srai    a5,a5,63
> >       and     a0,a1,a5
> > missing the opportunity to combine the NOT and AND into an ANDN.
> >
> > This adds a define_split to help the combiner reassociate the NOT with
> > the AND.
> >
> >
> > gcc/ChangeLog:
> >
> >       * config/riscv/bitmanip.md: New define_split.
> >
> > gcc/testsuite/ChangeLog:
> >
> >       * gcc.target/riscv/zbb-srai-andn.c: New test.
>
> OK.
>
>
> FWIW, combine can be pretty sneaky in manipulating the result of a scc
> style insn.    I've seen a port with pages and pages of special patterns
> to match what simplify_if_then_else would do.
>
>
> Jeff
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index b44fb9517e7..d26f3567182 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -128,6 +128,19 @@ 
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<X:MODE>")])
 
+;; '(a >= 0) ? b : 0' is emitted branchless (from if-conversion).  Without a
+;; bit of extra help for combine (i.e., the below split), we end up emitting
+;; not/srai/and instead of combining the not into an andn.
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(and:DI (neg:DI (ge:DI (match_operand:DI 1 "register_operand")
+			       (const_int 0)))
+		(match_operand:DI 2 "register_operand")))
+   (clobber (match_operand:DI 3 "register_operand"))]
+  "TARGET_ZBB"
+  [(set (match_dup 3) (ashiftrt:DI (match_dup 1) (const_int 63)))
+   (set (match_dup 0) (and:DI (not:DI (match_dup 3)) (match_dup 2)))])
+
 (define_insn "*xor_not<mode>"
   [(set (match_operand:X 0 "register_operand" "=r")
         (not:X (xor:X (match_operand:X 1 "register_operand" "r")
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-srai-andn.c b/gcc/testsuite/gcc.target/riscv/zbb-srai-andn.c
new file mode 100644
index 00000000000..afe9fba5f05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-srai-andn.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+
+long long foo0(long long a, long long b)
+{
+  if (a >= 0)
+    return b;
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "srai\t" 1 } } */
+/* { dg-final { scan-assembler-times "andn\t" 1 } } */
+