From patchwork Tue Nov 1 16:26:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Monakov X-Patchwork-Id: 1697795 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N1wQs6m0Lz23l6 for ; Wed, 2 Nov 2022 03:27:17 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8BF2338555A6 for ; Tue, 1 Nov 2022 16:27:15 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.ispras.ru (mail.ispras.ru [83.149.199.84]) by sourceware.org (Postfix) with ESMTPS id 197753858D35 for ; Tue, 1 Nov 2022 16:26:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 197753858D35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=ispras.ru Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ispras.ru Received: from localhost.intra.ispras.ru (unknown [10.10.3.121]) by mail.ispras.ru (Postfix) with ESMTP id DFC20419E9E6; Tue, 1 Nov 2022 16:26:55 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru DFC20419E9E6 From: Alexander Monakov To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/2] i386: correct x87&SSE division modeling in znver.md Date: Tue, 1 Nov 2022 19:26:36 +0300 Message-Id: <20221101162637.14238-2-amonakov@ispras.ru> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221101162637.14238-1-amonakov@ispras.ru> References: <20221101162637.14238-1-amonakov@ispras.ru> MIME-Version: 1.0 X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, MEDICAL_SUBJECT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Monakov , "Joshi, Tejas Sanjay" , =?utf-8?q?Jan_Hubi=C4=8Dka?= Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Correct modeling of division instructions in the SIMD/FP domain for AMD Zen architectures and avoid combinatorial explosion of automaton tables by modeling the separate floating-point division unit and correcting reservations to reflect reciprocal throughput of the corresponding instructions, similar to earlier commit 5cee5f94000 ("i386: correct integer division modeling in znver.md"). Division is partially pipelined and some instructions have fractional throughput (e.g. Zen 3 can issue divss and divsd each 3.5 and 4.5 cycles on average, respectively). Considering these CPUs implement out-of-order execution, the model doesn't need to be exact to the last cycle, so simplify it by using 4/5 cycles for SF/DF modes, and not modeling the fact that FP3 pipe is occupied for one cycle. Top znver table sizes in insn-automata.o: Before: 428108 r znver1_fp_min_issue_delay 856216 r znver1_fp_transitions After: 30056 r znver1_fp_min_issue_delay 120224 r znver1_fp_transitions gcc/ChangeLog: PR target/87832 * config/i386/znver.md (znver1_fdiv): New automaton. (znver1-fdiv): New unit. (znver1_fp_op_div): Correct unit and cycles in the reservation. (znver1_fp_op_div_load): Ditto. (znver1_fp_op_idiv_load): Ditto. (znver2_fp_op_idiv_load): Ditto. (znver1_ssediv_ss_ps): Ditto. (znver1_ssediv_ss_ps_load): Ditto. (znver1_ssediv_sd_pd): Ditto. (znver1_ssediv_sd_pd_load): Ditto. (znver1_ssediv_avx256_ps): Ditto. (znver1_ssediv_avx256_ps_load): Ditto. (znver1_ssediv_avx256_pd): Ditto. (znver1_ssediv_avx256_pd_load): Ditto. --- gcc/config/i386/znver.md | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/gcc/config/i386/znver.md b/gcc/config/i386/znver.md index 4aa098fd8..c52f8b532 100644 --- a/gcc/config/i386/znver.md +++ b/gcc/config/i386/znver.md @@ -24,7 +24,7 @@ (define_attr "znver1_decode" "direct,vector,double" ;; AMD znver1, znver2 and znver3 Scheduling ;; Modeling automatons for zen decoders, integer execution pipes, ;; SIMD/FP domain, AGU pipes, and dividers. -(define_automaton "znver1, znver1_ieu, znver1_fp, znver1_agu, znver1_idiv") +(define_automaton "znver1, znver1_ieu, znver1_fp, znver1_agu, znver1_idiv, znver1_fdiv") ;; Decoders unit has 4 decoders and all of them can decode fast path ;; and vector type instructions. @@ -95,6 +95,7 @@ (define_reservation "znver2-fvector" "znver1-fp0+znver1-fp1 ;; Dividers (define_cpu_unit "znver1-idiv" "znver1_idiv") +(define_cpu_unit "znver1-fdiv" "znver1_fdiv") ;; Call instruction (define_insn_reservation "znver1_call" 1 @@ -591,27 +592,27 @@ (define_insn_reservation "znver1_fp_op_div" 15 (and (eq_attr "cpu" "znver1,znver2,znver3") (and (eq_attr "type" "fdiv") (eq_attr "memory" "none"))) - "znver1-direct,znver1-fp3*15") + "znver1-direct,znver1-fdiv*6") (define_insn_reservation "znver1_fp_op_div_load" 22 (and (eq_attr "cpu" "znver1,znver2,znver3") (and (eq_attr "type" "fdiv") (eq_attr "memory" "load"))) - "znver1-direct,znver1-load,znver1-fp3*15") + "znver1-direct,znver1-load,znver1-fdiv*6") (define_insn_reservation "znver1_fp_op_idiv_load" 27 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "fdiv") (and (eq_attr "fp_int_src" "true") (eq_attr "memory" "load")))) - "znver1-double,znver1-load,znver1-fp3*19") + "znver1-double,znver1-load,znver1-fdiv*6") (define_insn_reservation "znver2_fp_op_idiv_load" 26 (and (eq_attr "cpu" "znver2,znver3") (and (eq_attr "type" "fdiv") (and (eq_attr "fp_int_src" "true") (eq_attr "memory" "load")))) - "znver1-double,znver1-load,znver1-fp3*19") + "znver1-double,znver1-load,znver1-fdiv*6") ;; MMX, SSE, SSEn.n, AVX, AVX2 instructions @@ -1088,7 +1089,7 @@ (define_insn_reservation "znver1_ssediv_ss_ps" 10 (eq_attr "mode" "V8SF,V4SF,SF"))) (and (eq_attr "type" "ssediv") (eq_attr "memory" "none"))) - "znver1-direct,znver1-fp3*10") + "znver1-direct,znver1-fdiv*4") (define_insn_reservation "znver1_ssediv_ss_ps_load" 17 (and (ior (and (eq_attr "cpu" "znver1") @@ -1099,7 +1100,7 @@ (define_insn_reservation "znver1_ssediv_ss_ps_load" 17 (eq_attr "mode" "V8SF,V4SF,SF"))) (and (eq_attr "type" "ssediv") (eq_attr "memory" "load"))) - "znver1-direct,znver1-load,znver1-fp3*10") + "znver1-direct,znver1-load,znver1-fdiv*4") (define_insn_reservation "znver1_ssediv_sd_pd" 13 (and (ior (and (eq_attr "cpu" "znver1") @@ -1110,7 +1111,7 @@ (define_insn_reservation "znver1_ssediv_sd_pd" 13 (eq_attr "mode" "V4DF,V2DF,DF"))) (and (eq_attr "type" "ssediv") (eq_attr "memory" "none"))) - "znver1-direct,znver1-fp3*13") + "znver1-direct,znver1-fdiv*5") (define_insn_reservation "znver1_ssediv_sd_pd_load" 20 (and (ior (and (eq_attr "cpu" "znver1") @@ -1121,35 +1122,35 @@ (define_insn_reservation "znver1_ssediv_sd_pd_load" 20 (eq_attr "mode" "V4DF,V2DF,DF"))) (and (eq_attr "type" "ssediv") (eq_attr "memory" "load"))) - "znver1-direct,znver1-load,znver1-fp3*13") + "znver1-direct,znver1-load,znver1-fdiv*5") (define_insn_reservation "znver1_ssediv_avx256_ps" 12 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V8SF") (and (eq_attr "memory" "none") (eq_attr "type" "ssediv")))) - "znver1-double,znver1-fp3*12") + "znver1-double,znver1-fdiv*8") (define_insn_reservation "znver1_ssediv_avx256_ps_load" 19 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V8SF") (and (eq_attr "type" "ssediv") (eq_attr "memory" "load")))) - "znver1-double,znver1-load,znver1-fp3*12") + "znver1-double,znver1-load,znver1-fdiv*8") (define_insn_reservation "znver1_ssediv_avx256_pd" 15 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V4DF") (and (eq_attr "type" "ssediv") (eq_attr "memory" "none")))) - "znver1-double,znver1-fp3*15") + "znver1-double,znver1-fdiv*10") (define_insn_reservation "znver1_ssediv_avx256_pd_load" 22 (and (eq_attr "cpu" "znver1") (and (eq_attr "mode" "V4DF") (and (eq_attr "type" "ssediv") (eq_attr "memory" "load")))) - "znver1-double,znver1-load,znver1-fp3*15") + "znver1-double,znver1-load,znver1-fdiv*10") ;; SSE MUL (define_insn_reservation "znver1_ssemul_ss_ps" 3 (and (ior (and (eq_attr "cpu" "znver1")