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[RFC,6/7] RISCV: Optimize Atomic Stores

Message ID 20220407183351.295188-7-patrick@rivosinc.com
State New
Headers show
Series RISCV: Implement ISA Manual Table A.6 Mappings | expand

Commit Message

Patrick O'Neill April 7, 2022, 6:33 p.m. UTC 
This change brings atomic stores in line with table A.6 of the ISA
manual.

2022-03-31 Patrick O'Neill <patrick@rivosinc.com>

	PR target/89835
	* riscv.cc (atomic_cas_value_strong<mode>): Add %I flag for
	atomic store fences.
	* sync.md (atomic_store<mode>): Use simple store instruction in
	combination with a fence.
	* pr89835.c: New test.
	
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
 gcc/config/riscv/riscv.cc                | 6 ++++++
 gcc/config/riscv/sync.md                 | 2 +-
 gcc/testsuite/gcc.target/riscv/pr89835.c | 9 +++++++++
 3 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6fbcd62fe73..48d18a83f06 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3677,6 +3677,7 @@  riscv_memmodel_needs_amo_release (enum memmodel model)
    'A'	Print the atomic operation suffix for memory model OP.
    'I'	Print the LR suffix for memory model OP.
    'J'	Print the SC suffix for memory model OP.
+   'K'  Print a leading fence for the memory model OP.
    'z'	Print x0 if OP is zero, otherwise print OP normally.
    'i'	Print i if the operand is not a register.
    'S'	Print shift-index of single-bit mask OP.
@@ -3728,6 +3729,11 @@  riscv_print_operand (FILE *file, rtx op, int letter)
 	fputs (".rl", file);
       break;
 
+    case 'K':
+      if (riscv_memmodel_needs_amo_release ((enum memmodel) INTVAL (op)))
+	fputs ("fence\trw,w;", file);
+      break;
+
     case 'i':
       if (code != REG)
         fputs ("i", file);
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index b54338d8eb2..1cc3731da38 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -65,7 +65,7 @@ 
        (match_operand:SI 2 "const_int_operand")]      ;; model
       UNSPEC_ATOMIC_STORE))]
   "TARGET_ATOMIC"
-  "amoswap.<amo>%A2 zero,%z1,%0"
+  "%K2s<amo>\t%z1,%0"
   [(set (attr "length") (const_int 4))])
 
 (define_insn "atomic_<atomic_optab><mode>"
diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/pr89835.c
new file mode 100644
index 00000000000..ab190e11b60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr89835.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* Verify that relaxed atomic stores use simple store instuctions.  */
+/* { dg-final { scan-assembler-not "amoswap" } } */
+
+void
+foo(int bar, int baz)
+{
+  __atomic_store_n(&bar, baz, __ATOMIC_RELAXED);
+}