From patchwork Wed Apr 6 06:55:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 1613797 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=Rac4kdUL; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KYFfd2lLkz9sFr for ; Wed, 6 Apr 2022 16:56:24 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D02123858407 for ; Wed, 6 Apr 2022 06:56:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D02123858407 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1649228181; bh=tHaH7VeKMGQDQfJZooGrCzHABdkKWMd1OHin82EY9qI=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=Rac4kdULE7IbMOm7jARTPG+MT6+TojMW+2zlxvIHr1xswMas1MkKiqGGhwQ/eO6Pu +OTraru76KGc74EZMkBqj80QCcB2pLV8h0KRWTwaNernn0Flrx7rc7HKN1s6ThQ8T/ xpP61XNRyF7ZoF7UOogjojy85Zh8x5XYJ/m0HWjY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id D14313858D37 for ; Wed, 6 Apr 2022 06:55:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D14313858D37 X-IronPort-AV: E=McAfee;i="6200,9189,10308"; a="285933954" X-IronPort-AV: E=Sophos;i="5.90,239,1643702400"; d="scan'208";a="285933954" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2022 23:55:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,239,1643702400"; d="scan'208";a="722389396" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga005.jf.intel.com with ESMTP; 05 Apr 2022 23:55:38 -0700 Received: from shliclel051.sh.intel.com (shliclel051.sh.intel.com [10.239.236.51]) by scymds01.sc.intel.com with ESMTP id 2366ta0C006972; Tue, 5 Apr 2022 23:55:37 -0700 To: gcc-patches@gcc.gnu.org Subject: [PATCH] Refine and/ior/xor/andn masked patterns for V*HFmode. Date: Wed, 6 Apr 2022 14:55:36 +0800 Message-Id: <20220406065536.15718-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" There's no masked vpandw or vpandb, similar for vpxor/vpor/vpandn. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,} Ready to push to trunk. gcc/ChangeLog: * config/i386/sse.md (_andnot3_mask): Removed. (_andnot3): Disable V*HFmode patterns for mask_applied. (3): Ditto. (*3): Ditto. (VFB_128_256): Adjust condition of V8HF/V16HFmode according to real instruction. (VFB_512): Ditto. --- gcc/config/i386/sse.md | 30 +++++++++++------------------- 1 file changed, 11 insertions(+), 19 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 1f9c496e7c0..92640aecc41 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -340,8 +340,7 @@ (define_mode_iterator VF_128_256 ;; 128- and 256-bit float vector modes for bitwise operations (define_mode_iterator VFB_128_256 - [(V16HF "TARGET_AVX512FP16") - (V8HF "TARGET_AVX512FP16") + [(V16HF "TARGET_AVX") (V8HF "TARGET_SSE2") (V8SF "TARGET_AVX") V4SF (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) @@ -399,7 +398,7 @@ (define_mode_iterator VF_512 ;; All 512bit vector float modes for bitwise operations (define_mode_iterator VFB_512 - [(V32HF "TARGET_AVX512FP16") V16SF V8DF]) + [V32HF V16SF V8DF]) (define_mode_iterator VI48_AVX512VL [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") @@ -4581,7 +4580,8 @@ (define_insn "_andnot3" (not:VFB_128_256 (match_operand:VFB_128_256 1 "register_operand" "0,x,v,v")) (match_operand:VFB_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] - "TARGET_SSE && " + "TARGET_SSE && + && (! || mode != HFmode)" { char buf[128]; const char *ops; @@ -4648,7 +4648,7 @@ (define_insn "_andnot3" (not:VFB_512 (match_operand:VFB_512 1 "register_operand" "v")) (match_operand:VFB_512 2 "nonimmediate_operand" "vm")))] - "TARGET_AVX512F" + "TARGET_AVX512F && (! || mode != HFmode)" { char buf[128]; const char *ops; @@ -4683,7 +4683,8 @@ (define_expand "3" (any_logic:VFB_128_256 (match_operand:VFB_128_256 1 "vector_operand") (match_operand:VFB_128_256 2 "vector_operand")))] - "TARGET_SSE && " + "TARGET_SSE && + && (! || mode != HFmode)" "ix86_fixup_binary_operands_no_copy (, mode, operands);") (define_expand "3" @@ -4691,7 +4692,7 @@ (define_expand "3" (any_logic:VFB_512 (match_operand:VFB_512 1 "nonimmediate_operand") (match_operand:VFB_512 2 "nonimmediate_operand")))] - "TARGET_AVX512F" + "TARGET_AVX512F && (! || mode != HFmode)" "ix86_fixup_binary_operands_no_copy (, mode, operands);") (define_insn "*3" @@ -4700,6 +4701,7 @@ (define_insn "*3" (match_operand:VFB_128_256 1 "vector_operand" "%0,x,v,v") (match_operand:VFB_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] "TARGET_SSE && + && (! || mode != HFmode) && !(MEM_P (operands[1]) && MEM_P (operands[2]))" { char buf[128]; @@ -4766,7 +4768,8 @@ (define_insn "*3" (any_logic:VFB_512 (match_operand:VFB_512 1 "nonimmediate_operand" "%v") (match_operand:VFB_512 2 "nonimmediate_operand" "vm")))] - "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" + "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2])) + && (! || mode != HFmode)" { char buf[128]; const char *ops; @@ -16738,17 +16741,6 @@ (define_expand "_andnot3_mask" (match_operand: 4 "register_operand")))] "TARGET_AVX512F") -(define_expand "_andnot3_mask" - [(set (match_operand:VI12_AVX512VL 0 "register_operand") - (vec_merge:VI12_AVX512VL - (and:VI12_AVX512VL - (not:VI12_AVX512VL - (match_operand:VI12_AVX512VL 1 "register_operand")) - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")) - (match_operand:VI12_AVX512VL 3 "nonimm_or_0_operand") - (match_operand: 4 "register_operand")))] - "TARGET_AVX512BW") - (define_insn "*andnot3" [(set (match_operand:VI 0 "register_operand" "=x,x,v") (and:VI